公开(公告)号：US11995263B1

公开(公告)日：2024-05-28

申请号：US17033236

申请日：2020-09-25

Applicant: Apple Inc.

Inventor： Hung Sheng Lin ,  Jun Qi ,  Hao-Lin Chiu ,  Sai-Chang Liu

IPC: G06F3/041 ,  G06F1/16 ,  G06F3/044

CPC classification number: G06F3/04166 ,  G06F1/1643 ,  G06F3/0412 ,  G06F3/0445 ,  G06F3/0448

Abstract: A touch screen may be formed from a display and perimeter touch electrodes. Touches detected at one or more of the perimeter touch electrodes can be imputed to touch on a region of the display of the touch screen adjacent to the perimeter touch electrodes. In some examples, the perimeter touch electrodes comprise segmented frit metal arranged around the perimeter of the display (e.g., frit metal used to encapsulate the display). In some examples, the perimeter touch electrodes can be coupled to one or more touch sensing circuits via switching circuitry. In some examples, the switching circuitry can be operated based on control signals shared with the display circuitry.

公开(公告)号：US10955947B2

公开(公告)日：2021-03-23

申请号：US15493791

申请日：2017-04-21

Applicant: Apple Inc.

Inventor： Patrick Bennett ,  Byung Duk Yang ,  Chun-Yao Huang ,  Hao-Lin Chiu ,  Ivan Knez ,  Peien Chang ,  Rungrot Kitsomboonloha ,  Shih-Chang Chang ,  Shinya Ono ,  Szuhsien Lee

IPC: G06F3/041 ,  G06F3/044

Abstract: A touch sensor panel comprising a first touch node electrode of a plurality of touch node electrodes, the first touch node electrode coupled to a first sense connection comprising a first set of traces, the first sense connection configured to have a first resistance per unit length that varies along a length of the first sense connection, and a second touch node electrode of the plurality of touch node electrodes, the second touch node electrode coupled to a second sense connection comprising a second set of traces, the second sense connection configured to have a second resistance per unit length that varies along a length of the second sense connection differently than the first resistance per unit length varies along the length of the first sense connection. An effective resistance of the first sense connection and the second sense connection are equal.

公开(公告)号：US09727167B2

公开(公告)日：2017-08-08

申请号：US14923246

申请日：2015-10-26

Applicant: Apple Inc.

Inventor： Byung Duk Yang ,  Szu-Hsien Lee ,  Kyung Wook Kim ,  Shih Chang Chang ,  Chun-Yao Huang ,  Hao-Lin Chiu

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/36 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12

CPC classification number: G09G3/3648 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13456 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04104 ,  G06F2203/04112 ,  G09F9/30 ,  G09G3/3666 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0281 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

公开(公告)号：US20240420643A1

公开(公告)日：2024-12-19

申请号：US18654541

申请日：2024-05-03

Applicant: Apple Inc.

Inventor： Hao-Lin Chiu ,  Chin-Wei Lin ,  Shinya Ono ,  Kyung Wook Kim ,  Szu-Hsien Lee ,  Pei-En Chang ,  Kwang Soon Park

IPC: G09G3/3266 ,  H01L27/12 ,  H01L29/786

Abstract: A driver circuit configured to output a control signal to a row of display pixels is provided. The driver circuit can include a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit on which the control signal is generated and a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line. The first and second transistors can be coupled to a plurality of transistors coupled between a second positive power supply line and a second ground power supply line, configured to receive one or more clocks signals, and at least some of which include bottom gate terminals.

公开(公告)号：US20190228732A1

公开(公告)日：2019-07-25

申请号：US16147045

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Pei-Yu Hou ,  Yang Li ,  Hao-Lin Chiu

IPC: G09G3/36

Abstract: A display includes a plurality of pixels grouped into a plurality of lines of pixels. Each line of pixels of the plurality of lines comprises a group of pixels of the plurality of pixels that are coupled to a common scan line as well and that are coupled to different data lines to individually activate each pixel of the group of pixels. The display also includes a common voltage (VCOM) driving circuit configured to receive a waveform and drive the waveform to the display as a VCOM having a value tailored to an individually activated pixel of the group of pixels.

公开(公告)号：US20190086720A1

公开(公告)日：2019-03-21

申请号：US16041667

申请日：2018-07-20

Applicant: Apple Inc.

Inventor： Byung Duk Yang ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Kyung Wook Kim ,  Sai-Chang Liu ,  Shih Chang Chang

IPC: G02F1/1335 ,  G02F1/133 ,  G02F1/1334 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/136209 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/133357 ,  G02F2001/136222 ,  G02F2001/13685

Abstract: A display may have pixels configured to display images. The pixels may be formed from thin-film transistor circuitry on a substrate. Color filter elements formed from colored polymer such as colored photoimageable polymer may be formed on the substrate. A black matrix formed from black photoimageable polymer may have an array of openings. The colored polymer may have first portions that overlap the black matrix and second portions in the openings that form the color filter elements. In some portions of the pixels, the thin-film transistor circuitry may be interposed between the first portions of the colored polymer and the black matrix. In other portions of the pixels, data lines may be formed that are overlapped by the black matrix and that are interposed between the first portions of the colored polymer and the black matrix.

公开(公告)号：US10008139B2

公开(公告)日：2018-06-26

申请号：US14995796

申请日：2016-01-14

Applicant: APPLE INC.

Inventor： Howard H. Tang ,  Wei Chen ,  Paolo Sacchetto ,  Chaohao Wang ,  Chun-Yao Huang ,  Hao-Lin Chiu

IPC: G09G3/36 ,  G09G3/00 ,  G09G3/20

CPC classification number: G09G3/00 ,  G09G3/20 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/0278 ,  G09G2310/0281 ,  G09G2320/0209 ,  G09G2320/0219

Abstract: A display device may include a plurality of pixels, a plurality of source lines that may provide a plurality of data line signals to the plurality of pixels, a plurality of gate lines that may provide a plurality of gate signals to a plurality of switches associated with the plurality of pixels, and a plurality of voltage gate lines disposed parallel to the plurality of source lines and coupled to the plurality of gate lines at a plurality of cross point nodes. The plurality of cross point nodes are positioned in a pseudo random order across the display device.

公开(公告)号：US20160098144A1

公开(公告)日：2016-04-07

申请号：US14923246

申请日：2015-10-26

Applicant: Apple Inc.

Inventor： Byung Duk Yang ,  Szu-Hsien Lee ,  Kyung Wook Kim ,  Shih Chang Chang ,  Chun-Yao Huang ,  Hao-Lin Chiu

IPC: G06F3/041 ,  G09G3/36 ,  G06F3/044

CPC classification number: G09G3/3648 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13456 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04104 ,  G06F2203/04112 ,  G09F9/30 ,  G09G3/3666 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0281 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

Abstract translation: 显示器可以具有排列成行和列的像素阵列。 每个像素可以具有用于控制与该像素相关联的输出光量的晶体管。 晶体管可以是具有有源区的薄膜晶体管，第一和第二源极 - 漏极端子和栅极。 栅极线可用于将栅极控制信号分配到每行中的晶体管的栅极。 垂直于栅极线延伸的数据线可用于沿像素列分布图像数据。 栅极线可以连接到平行于数据线延伸的栅极线扩展。 数据线可以各自重叠相应的一个栅极线延伸。 通孔可用于将栅极线延伸部分连接到栅极线。 门线扩展可能都具有相同的长度。

公开(公告)号：US08987049B2

公开(公告)日：2015-03-24

申请号：US14474433

申请日：2014-09-02

Applicant: Apple Inc.

Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract translation: 提供了制造薄膜晶体管（TFT）的方法。 该方法包括在覆盖栅电极的栅极绝缘体上形成半导体层，以及在半导体层上沉积绝缘体层，以及蚀刻绝缘体层以形成图案化蚀刻停止件，而不会失去栅极绝缘体。 该方法还包括在半导体层和图案化蚀刻停止物上形成源电极和漏电极。 该方法还包括：除了源电极和漏电极之外的半导体层的一部分，使得半导体层的剩余部分在源电极和栅电极的第一重叠区域和第二重叠区域中覆盖栅极绝缘体 的漏电极和栅电极。

公开(公告)号：US20140042427A1

公开(公告)日：2014-02-13

申请号：US13629537

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract translation: 提供了制造薄膜晶体管（TFT）的方法。 该方法包括在覆盖栅电极的栅极绝缘体上形成半导体层，以及在半导体层上沉积绝缘体层，以及蚀刻绝缘体层以形成图案化蚀刻停止件，而不会失去栅极绝缘体。 该方法还包括在半导体层和图案化蚀刻停止物上形成源电极和漏电极。 该方法还包括：除了源电极和漏电极之外的半导体层的一部分，使得半导体层的剩余部分在源电极和栅电极的第一重叠区域和第二重叠区域中覆盖栅极绝缘体 的漏电极和栅电极。