公开(公告)号：US10761561B2

公开(公告)日：2020-09-01

申请号：US15989228

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Saira Samar Malik ,  David Joseph Hawkins ,  Andrew David Tune ,  Guanghui Geng ,  Julian Jose Hilgemberg Pontes

IPC: G06F1/12 ,  G06F30/39

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

公开(公告)号：US10713187B2

公开(公告)日：2020-07-14

申请号：US16521621

申请日：2019-07-25

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Paul Gilbert Meyer ,  David Joseph Hawkins ,  Phanindra Kumar Mannava ,  Joseph Michael Pusdesris

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0831 ,  G06F12/0844

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

公开(公告)号：US11181957B1

公开(公告)日：2021-11-23

申请号：US17102963

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Ramamoorthy Guru Prasadh ,  Tushar P Ringe ,  Kishore Kumar Jagadeesha ,  David Joseph Hawkins ,  Saira Samar Malik

IPC: G06F1/24 ,  H03K19/20 ,  G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K5/00

Abstract: An improved apparatus and method for the protection of reset in systems with stringent safety goals that employ primary and shadow logic blocks with a lock-step checker to achieve functional safety, including those systems having very large fanout of primary and shadow reset signal trees. The disclosed apparatus and method support assertion of reset that is asynchronous to the system clock and deassertion of reset that is synchronous to the system clock. Shadow logic blocks have reset deasserted a fixed number of clock cycles after their respective primary logic blocks, thereby avoiding the requirement to synchronize the primary and shadow reset signal trees at each of their end points to ensure lock-step operation between the primary and shadow logic blocks.

公开(公告)号：US11520626B2

公开(公告)日：2022-12-06

申请号：US17028422

申请日：2020-09-22

Applicant: Arm Limited

Inventor： Michael Andrew Campbell ,  Peter Owen Hawkins ,  David Joseph Hawkins

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/54 ,  G06F9/52 ,  G06F9/50

Abstract: A method and system for an enhanced weighted fair queuing technique for a resource are provided. A plurality of request streams is received at a requestor, each request stream including request messages from a process executing on the requestor. The request messages of each request stream are apportioned to an input queue associated with the request stream; each input queue has a weight. A virtual finish time is determined for each request message based, at least in part, on the weights of the input queues. A sequence of request messages is determined based, at least in part, on the virtual finish times of the request messages. The sequence of request messages is enqueued into an output queue. The sequence of request messages is sent to a resource, over a connection, which provides a service for each process.

公开(公告)号：US20220091886A1

公开(公告)日：2022-03-24

申请号：US17028422

申请日：2020-09-22

Applicant: Arm Limited

Inventor： Michael Andrew Campbell ,  Peter Owen Hawkins ,  David Joseph Hawkins

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06F9/54

Abstract: A method and system for an enhanced weighted fair queuing technique for a resource are provided. A plurality of request streams is received at a requestor, each request stream including request messages from a process executing on the requestor. The request messages of each request stream are apportioned to an input queue associated with the request stream; each input queue has a weight. A virtual finish time is determined for each request message based, at least in part, on the weights of the input queues. A sequence of request messages is determined based, at least in part, on the virtual finish times of the request messages. The sequence of request messages is enqueued into an output queue. The sequence of request messages is sent to a resource, over a connection, which provides a service for each process.

公开(公告)号：US10402349B2

公开(公告)日：2019-09-03

申请号：US15427391

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Paul Gilbert Meyer ,  David Joseph Hawkins ,  Phanindra Kumar Mannava ,  Joseph Michael Pusdesris

IPC: G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0831 ,  G06F12/0844

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.