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公开(公告)号：US11526305B2
公开(公告)日：2022-12-13
申请号：US17103629
申请日：2020-11-24
Applicant: Arm Limited
Inventor： Mudit Bhargava , Paul Nicholas Whatmough , Supreet Jeloka , Zhi-Gang Liu
Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of read word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each read word selector has a plurality of input ports and an output port, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the read word selectors of the first bank and the second bank, and configured to select a combination of read word selectors from at least one of the first bank and the second bank based on a bank select signal.
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公开(公告)号：US20220343045A1
公开(公告)日：2022-10-27
申请号：US17497400
申请日：2021-10-08
Applicant: Arm Limited
Inventor： Rainer Herberholz , Supreet Jeloka
IPC: G06F30/3312
Abstract: Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.
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公开(公告)号：US20220172762A1
公开(公告)日：2022-06-02
申请号：US17107725
申请日：2020-11-30
Applicant: Arm Limited
Inventor： Supreet Jeloka , Mudit Bhargava , Pranay Prabhat , Femando Garcia Redondo
IPC: G11C11/16
Abstract: Various implementations described herein are related to a method. The method may apply a write control voltage to a bitcell. The method may gradually ramp the write control voltage to the bitcell. The method may terminate application of the write control voltage to the bitcell when a write operation is sensed in the bitcell.
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公开(公告)号：US11211111B1
公开(公告)日：2021-12-28
申请号：US17038795
申请日：2020-09-30
Applicant: Arm Limited
Inventor： Rahul Mathur , Mudit Bhargava , Supreet Jeloka , Andy Wangkun Chen
IPC: G11C11/40 , G11C11/4076 , G11C11/4094 , G11C5/02 , G11C15/04 , G11C11/4097
Abstract: A content-addressable memory (CAM) storage element includes bit storage cell bit comparison cells. The bit storage cell is arranged on a first die tier and includes at least one transistor, one or two bit lines, and a storage node. The bit comparison cell is arranged on a second die tier and has a match line, complementary search lines, and at least three transistors. The complementary search lines are decoupled from the bit line(s). A 3D connection couples the storage node to one of the transistors of the second die tier. The CAM cell performs at least one CAM search per clock cycle using at least four transistors per search, including the at least one transistor of the bit storage cell and the at least three transistors of the bit comparison cell, and to output results of the at least one CAM search on the match line.
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公开(公告)号：US12159659B2
公开(公告)日：2024-12-03
申请号：US17107725
申请日：2020-11-30
Applicant: Arm Limited
Inventor： Supreet Jeloka , Mudit Bhargava , Pranay Prabhat , Fernando Garcia Redondo
IPC: G11C11/16
Abstract: Various implementations described herein are related to a method. The method may apply a write control voltage to a bitcell. The method may gradually ramp the write control voltage to the bitcell. The method may terminate application of the write control voltage to the bitcell when a write operation is sensed in the bitcell.
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Patent Agency Ranking
公开(公告)号：US12061853B2
公开(公告)日：2024-08-13
申请号：US17497400
申请日：2021-10-08
Applicant: Arm Limited
Inventor： Rainer Herberholz , Supreet Jeloka
IPC: G06F30/3312 , G06F111/04 , G06F119/12
CPC classification number: G06F30/3312 , G06F2111/04 , G06F2119/12
Abstract: Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.
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公开(公告)号：US11521680B2
公开(公告)日：2022-12-06
申请号：US17139059
申请日：2020-12-31
Applicant: Arm Limited
Inventor： Fernando Garcia Redondo , Mudit Bhargava , Pranay Prabhat , Supreet Jeloka
Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.
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公开(公告)号：US11966785B2
公开(公告)日：2024-04-23
申请号：US16943117
申请日：2020-07-30
Applicant: Arm Limited
Inventor： Dam Sunwoo , Supreet Jeloka , Saurabh Pijuskumar Sinha , Jaekyu Lee , Jose Alberto Joao , Krishnendra Nathella
CPC classification number: G06F9/5044 , G06F9/5038 , G06F9/505 , G06N5/04 , G06N20/00
Abstract: A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.
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公开(公告)号：US11693796B2
公开(公告)日：2023-07-04
申请号：US17334960
申请日：2021-05-31
Applicant: Arm Limited
Inventor： Paul Nicholas Whatmough , Zhi-Gang Liu , Supreet Jeloka , Saurabh Pijuskumar Sinha , Matthew Mattina
CPC classification number: G06F13/1668 , G06F13/4004 , G06F7/5443 , G06F15/8046 , G06N3/063
Abstract: Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.
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公开(公告)号：US20220391469A1
公开(公告)日：2022-12-08
申请号：US17339895
申请日：2021-06-04
Applicant: Arm Limited
Inventor： Supreet Jeloka , Mudit Bhargava , Saurabh Pijuskumar Sinha , Rahul Mathur
Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.
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