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    DETECTION OF ABNORMAL OR MALICIOUS ACTIVITY IN POINT-TO-POINT OR PACKET-SWITCHED NETWORKS
    2.
    发明申请
    DETECTION OF ABNORMAL OR MALICIOUS ACTIVITY IN POINT-TO-POINT OR PACKET-SWITCHED NETWORKS 有权

    公开(公告)号：US20220141237A1

    公开(公告)日：2022-05-05

    申请号：US17090275

    申请日：2020-11-05

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： Richard J. Ferguson ,  Michael Bear ,  Sumit Ray ,  Jeannine Robertazzi ,  Daniel L. Stanley

    IPC: H04L29/06 ,  H04L29/08

    Abstract: A method of detecting abnormal or malicious activity in a point-to-point or packet-switched data communication network includes tapping a link in the network to obtain a data stream transmitted from a node of the network in parallel with transmission of the data stream through the network. The tap is non-invasive because it does not interfere with the normal traversal of the data stream across the network. This is useful for certain applications, such as mission-critical systems, where it is desirable to monitor the network and inspect the data without adversely impacting or otherwise interfering with the normal operation of the system. The method further includes decoding a communication protocol encoded in the data stream to obtain payload data from the data stream, analyzing the payload data to detect abnormal or malicious activity, and notifying a host of the network of the detected abnormal or malicious activity in the payload data.

    FIREWALL FOR ON-CHIP SIGNALING
    3.
    发明公开
    FIREWALL FOR ON-CHIP SIGNALING 审中-公开

    公开(公告)号：US20230244824A1

    公开(公告)日：2023-08-03

    申请号：US17591699

    申请日：2022-02-03

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： David D. Moser ,  Daniel L. Stanley ,  Tate J. Keegan ,  Joshua C. Schabel ,  Sheldon L. Grass

    IPC: G06F21/85 ,  G06F12/14

    CPC classification number: G06F21/85 ,  G06F12/1458 ,  G06F2212/1052

    Abstract: An on-chip firewall circuit for providing secure on-chip communication is disclosed. The firewall circuit includes a configurable table of port IDs along with a configurable setting for each port ID to either provide the corresponding port ID with open access to the components of a secure enclave (SE) module or restricted access. If access is restricted, then the command is rerouted to a portion of the secure memory within the SE module, where it can be read only via a secure processing device within the SE module. The secure processing device may require additional verification of the port ID before executing the command stored within the secure memory. In this way, unsecure devices from outside of the SE module can be configured to have no direct access to any of the components within the SE module.

    SEMICONDUCTOR DEVICE WITH REDACTED LOGIC
    5.
    发明申请
    SEMICONDUCTOR DEVICE WITH REDACTED LOGIC 有权

    公开(公告)号：US20250077755A1

    公开(公告)日：2025-03-06

    申请号：US18456648

    申请日：2023-08-28

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： David D. Moser ,  Daniel L. Stanley ,  Jane O. Gilliam

    IPC: G06F30/343

    Abstract: A semiconductor device includes a data port, a programmable logic block for executing a manufacturer test, and a processor operatively coupled to the data port. The processor is configured to assert, in a first modality, a configuration isolation signal to the data port. The data port is configured to be communicatively isolated from the programmable logic block while the configuration isolation signal is asserted. The processor is configured to de-assert, in a second modality, the configuration isolation signal from the data port. The data port is configured to be communicatively coupled to the programmable logic block while the configuration isolation signal is de-asserted. In some examples, the semiconductor device includes a communication interface communicatively coupled to the programmable logic block, wherein the processor is further configured to cause, in the first modality, data to be loaded into the programmable logic block from a first-in-first-out (FIFO) buffer of the communication interface.

    Triple modular redundancy (TMR) radiation hardened memory system
    6.
    发明授权
    Triple modular redundancy (TMR) radiation hardened memory system 有权

    公开(公告)号：US11861181B1

    公开(公告)日：2024-01-02

    申请号：US17818850

    申请日：2022-08-10

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： David D. Moser ,  Richard J. Ferguson ,  Daniel L. Stanley

    IPC: G06F11/07 ,  G06F3/06 ,  G06F11/14

    CPC classification number: G06F3/0619 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/0772 ,  G06F11/141

    Abstract: Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.

    SECURE SEMICONDUCTOR AND SYSTEM DESIGN
    9.
    发明公开
    SECURE SEMICONDUCTOR AND SYSTEM DESIGN 审中-公开

    公开(公告)号：US20240202375A1

    公开(公告)日：2024-06-20

    申请号：US17907020

    申请日：2022-03-24

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： David D. Moser ,  Daniel L. Stanley ,  Joshua C. Schabel ,  Tate J. Keegan ,  Sheldon L. Grass

    IPC: G06F21/76 ,  G06F30/347

    CPC classification number: G06F21/76 ,  G06F30/347

    Abstract: A secure system includes a data port, a network on chip (NoC) module, a processor communicatively coupled to the NoC module, a communication interface operatively coupled to the processor and to the data port, an electronic field-programmable gate array (eFPGA) configuration module operatively coupled to the NoC module, and a clock operatively coupled to the NoC module. In a first modality, the communication interface is at least partially disabled. In a second modality, the communication interface is at least partially disabled, boundary scan operations are disabled, a RESET signal is held in a constant state, and/or redacted code is rendered inoperable. In a third modality, the communication interface is at least partially enabled to send and receive commands and data via the data port, the boundary scan operations are enabled, the RESET signal is not held in the constant state, and/or the redacted code is operable.

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