公开(公告)号：US20170194448A1

公开(公告)日：2017-07-06

申请号：US15313141

申请日：2016-03-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangyong KONG ,  Lung Pao HSIN ,  Jun CHENG

IPC: H01L29/45 ,  H01L21/311 ,  H01L29/417 ,  H01L21/4757 ,  H01L29/66 ,  H01L21/768 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L21/31144 ,  H01L21/47573 ,  H01L21/76802 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

Abstract: Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a base substrate, a first electrode pattern, a second electrode pattern, and an active layer pattern disposed on the base substrate, a first electrode protection pattern coating the first electrode pattern, and a second electrode protection pattern coating the second electrode pattern. The active layer pattern is disposed between the first electrode pattern and the second electrode pattern. The first electrode protection pattern and the second electrode protection pattern are connected to two sides of the active layer pattern, respectively. The problem that, the active layer pattern cannot be connected to the first electrode pattern and the second electrode pattern due to the surface oxidation, when the first electrode pattern and the second electrode pattern adopt material with low resistance characteristic, is avoided, thus increasing the product yield.

公开(公告)号：US20170040343A1

公开(公告)日：2017-02-09

申请号：US14912822

申请日：2015-08-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lung Pao HSIN

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/51

CPC classification number: H01L27/124 ,  H01L21/77 ,  H01L27/02 ,  H01L29/06 ,  H01L29/41733 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/786

Abstract: A thin film transistor and a fabrication method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a gate electrode (2), a source electrode (5) and a drain electrode (6) disposed in a same layer on a base substrate (1); a gate insulating layer (3) disposed on the gate electrode (2), the source electrode (5) and the drain electrode (6); an active layer (4) disposed on the gate insulating layer (3); a passivation layer (7) disposed on the active layer (4) and the gate insulating layer (3). A first via hole (81) and a second via hole (91) are disposed in the passivation layer (7); a third via hole (82) and a fourth via hole (92) are disposed in the passivation layer (7) and the gate insulating layer (3); a first connection pattern (8) and a second connection pattern (9) are disposed on the passivation layer (7); the first connection pattern (8) is connected with the active layer (4) and the source electrode (5) through the first via hole (81) and the third via hole (82) respectively; the second connection pattern (9) is connected with the active layer (4) and the drain electrode (6) through the second via hole (91) and the fourth via hole (92) respectively. The thin film transistor effectively reduces the influence of the parasitic capacitance between the source electrode and the gate electrode and the parasitic capacitance between the drain electrode and the gate electrode on the thin film transistor.

Abstract translation: 提供薄膜晶体管及其制造方法，阵列基板和显示面板。 薄膜晶体管包括：设置在基底基板（1）上的同一层中的栅电极（2），源电极（5）和漏电极（6）。 设置在栅电极（2）上的栅极绝缘层（3），源电极（5）和漏电极（6）; 设置在栅极绝缘层（3）上的有源层（4）; 设置在有源层（4）和栅极绝缘层（3）上的钝化层（7）。 第一通孔（81）和第二通孔（91）设置在钝化层（7）中; 在钝化层（7）和栅极绝缘层（3）中设置第三通孔（82）和第四通孔（92）。 第一连接图案（8）和第二连接图案（9）设置在钝化层（7）上; 第一连接图案（8）分别通过第一通孔（81）和第三通孔（82）与有源层（4）和源电极（5）连接; 第二连接图案（9）分别通过第二通孔（91）和第四通孔（92）与有源层（4）和漏电极（6）连接。 薄膜晶体管有效地减小了源电极和栅电极之间的寄生电容以及薄膜晶体管上的漏电极和栅电极之间的寄生电容的影响。

公开(公告)号：US20160043228A1

公开(公告)日：2016-02-11

申请号：US14770369

申请日：2014-11-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunsheng JIANG ,  Lung Pao HSIN

IPC: H01L29/786 ,  H01L21/441 ,  H01L21/02 ,  H01L27/12 ,  H01L21/425 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L21/02565 ,  H01L21/425 ,  H01L21/441 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/127 ,  H01L29/0684 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and a display apparatus are disclosed. The manufacturing method includes forming a gate electrode (2), a gate insulating layer (3), an active region (4), a source electrode (5) and a drain electrode (6) on a base substrate (1) with the active region being formed of ZnON material, and implanting the active region (4) with nitrogen ion while it being formed, so as to make the sub-threshold swing amplitude of the thin film transistor less than or equal to 0.5 mV/dec. The manufacturing method reduces the sub-threshold swing amplitude of the thin film transistor and improves the semiconductor characteristics of the thin film transistor.

Abstract translation: 公开了一种薄膜晶体管，其制造方法，阵列基板和显示装置。 制造方法包括在基板（1）上形成栅电极（2），栅极绝缘层（3），有源区（4），源电极（5）和漏电极（6） 区域由ZnON材料形成，并且在形成有源区域（4）时形成氮离子，以使薄膜晶体管的次阈值摆动振幅小于或等于0.5mV / dec。 制造方法降低了薄膜晶体管的次阈摆幅，提高了薄膜晶体管的半导体特性。

公开(公告)号：US20170148366A1

公开(公告)日：2017-05-25

申请号：US15113340

申请日：2016-01-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lung Pao HSIN ,  Junjie LIN

IPC: G09G3/20 ,  H01L27/32 ,  H01L51/56 ,  G09G3/3225

CPC classification number: G09G3/2003 ,  G09G3/2074 ,  G09G3/3225 ,  G09G2300/0443 ,  G09G2300/0809 ,  H01L27/3213 ,  H01L27/3246 ,  H01L27/3262 ,  H01L51/56 ,  H01L2251/558

Abstract: Embodiments of the present invention relate to a display substrate and fabricating method thereof and a display device. The display substrate comprises a plurality of pixel groups, wherein each of said pixel groups comprises a plurality of color sub-pixels and a plurality of white sub-pixels. A first driving transistor is provided in a light emitting layer missing region of the color sub-pixel, for driving the color sub-pixel. A second driving transistor and a white sub-pixel are provided on the first driving transistor, the second driving transistor for driving the white sub-pixel. According to the technical solution, white light OLED display may be implemented by forming the white sub-pixel and the driving transistor thereof on the driving transistor of the color sub-pixel, while making use of the space on the thickness dimension of the color sub-pixel, so that the light emitting layer missing region in the color sub-pixel is fully utilized.