公开(公告)号：US20060044232A1

公开(公告)日：2006-03-02

申请号：US11210743

申请日：2005-08-25

申请人： Beohm-Rock Choi ,  Hee-Hwan Choe ,  Chong-Chul Chai

发明人： Beohm-Rock Choi ,  Hee-Hwan Choe ,  Chong-Chul Chai

IPC分类号： G09G3/30

CPC分类号： H01L27/3244 ,  G09G3/3225 ,  G09G2300/0842 ,  H01L27/3276

摘要： An organic light emitting diode display including a light emitting element, a first conductive line, a second conductive line, and a third conductive line separated from one another, and a first thin film transistor coupled to the third conductive line and the light emitting element and a second thin film transistor coupled to the first conductive line and the second conductive line. A third thin film transistor includes a first electrode and a fourth thin film transistor includes a second electrode, and the first electrode and the second electrode are coupled to each other through a first contact hole in a first insulating layer.

摘要翻译： 一种有机发光二极管显示器，包括发光元件，第一导电线，第二导线和彼此分离的第三导线，以及耦合到第三导线和发光元件的第一薄膜晶体管， 耦合到第一导线和第二导线的第二薄膜晶体管。 第三薄膜晶体管包括第一电极，第四薄膜晶体管包括第二电极，第一电极和第二电极通过第一绝缘层中的第一接触孔相互耦合。

公开(公告)号：US07482208B2

公开(公告)日：2009-01-27

申请号：US10572234

申请日：2004-09-16

申请人： Sang-Gab Kim ,  Je-Min Lee ,  Gwan-Young Cho ,  Jong-Tae Jeong ,  In-Ho Song ,  Hee-Hwan Choe ,  Sung-Chul Kang ,  Ho-Min Kang ,  Beohm-Rock Choi ,  Joon-Hoo Choi

发明人： Sang-Gab Kim ,  Je-Min Lee ,  Gwan-Young Cho ,  Jong-Tae Jeong ,  In-Ho Song ,  Hee-Hwan Choe ,  Sung-Chul Kang ,  Ho-Min Kang ,  Beohm-Rock Choi ,  Joon-Hoo Choi

IPC分类号： H01L21/00 ,  H01L21/302

CPC分类号： G02F1/13439 ,  G02F1/1345 ,  G02F1/136227 ,  G02F2001/13629 ,  H01L27/322 ,  H01L27/3244 ,  H01L27/3276 ,  H01L51/5215 ,  H01L2251/558

摘要： The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention provides pixel electrodes and contact assistants, which connect expansions of gate lines and data lines to an external circuit, having a structure of double layers including IZO layer and ITO layer. The ITO layer is disposed on the IZO layer. In the present invention, the pixel electrodes are formed to have double layers of IZO layer and ITO layer to avoid wires from getting damage by the ITO etchant and to prevent prove pins from having accumulation of foreign body during the gross test. In the present invention, the contact assistants may only be formed to have double layers of IZO layer and ITO layer to prevent prove pins from having accumulation of foreign body during the gross test. Since the consumption of ITO is reduced, manufacturing cost decreases.

摘要翻译： 本发明涉及薄膜晶体管阵列面板，液晶显示器及其制造方法。 用于LCD或EL显示器的TFT阵列用作用于独立地驱动各个像素的电路板。 本发明提供了将栅极线和数据线的扩展连接到外部电路的像素电极和接触辅助件，其具有包括IZO层和ITO层的双层结构。 ITO层设置在IZO层上。 在本发明中，像素电极形成为具有双层IZO层和ITO层，以避免电线被ITO蚀刻剂损坏，并且防止在总体测试期间引脚不会积累异物。 在本发明中，接触助剂只能形成为具有双层IZO层和ITO层，以防止在总体测试期间引脚不会积累异物。 由于ITO的消耗减少，制造成本降低。

公开(公告)号：US20070065991A1

公开(公告)日：2007-03-22

申请号：US10572234

申请日：2004-09-16

申请人： Sang-Gab Kim ,  Je-Min Lee ,  Gwan-Young Cho ,  Jong-Tae Jeong ,  In-Ho Song ,  Hee-Hwan Choe ,  Sung-Chul Kang ,  Ho-Min Kang ,  Beohm-Rock Choi ,  Joon-Hoo Choi

发明人： Sang-Gab Kim ,  Je-Min Lee ,  Gwan-Young Cho ,  Jong-Tae Jeong ,  In-Ho Song ,  Hee-Hwan Choe ,  Sung-Chul Kang ,  Ho-Min Kang ,  Beohm-Rock Choi ,  Joon-Hoo Choi

IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L31/00 ,  G02F1/1343

CPC分类号： G02F1/13439 ,  G02F1/1345 ,  G02F1/136227 ,  G02F2001/13629 ,  H01L27/322 ,  H01L27/3244 ,  H01L27/3276 ,  H01L51/5215 ,  H01L2251/558

摘要： The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention provides pixel electrodes and contact assistants, which connect expansions of gate lines and data lines to an external circuit, having a structure of double layers including IZO layer and ITO layer. The ITO layer is disposed on the IZO layer. In the present invention, the pixel electrodes are formed to have double layers of IZO layer and ITO layer to avoid wires from getting damage by the ITO etchant and to prevent prove pins from having accumulation of foreign body during the gross test. In the present invention, the contact assistants may only be formed to have double layers of IZO layer and ITO layer to prevent prove pins from having accumulation of foreign body during the gross test. Since the consumption of ITO is reduced, manufacturing cost decreases.

摘要翻译： 本发明涉及薄膜晶体管阵列面板，液晶显示器及其制造方法。 用于LCD或EL显示器的TFT阵列用作用于独立地驱动各个像素的电路板。 本发明提供了将栅极线和数据线的扩展连接到外部电路的像素电极和接触辅助件，其具有包括IZO层和ITO层的双层结构。 ITO层设置在IZO层上。 在本发明中，像素电极形成为具有双层IZO层和ITO层，以避免电线被ITO蚀刻剂损坏，并且防止在总体测试期间引脚不会积累异物。 在本发明中，接触助剂只能形成为具有双层IZO层和ITO层，以防止在总体测试期间引脚不会积累异物。 由于ITO的消耗减少，制造成本降低。

公开(公告)号：US07501297B2

公开(公告)日：2009-03-10

申请号：US11336087

申请日：2006-01-20

申请人： Jang-Soo Kim ,  Soo-Jin Kim ,  Kyoung-Tai Han ,  Hee-Hwan Choe ,  Joo-Han Kim

发明人： Jang-Soo Kim ,  Soo-Jin Kim ,  Kyoung-Tai Han ,  Hee-Hwan Choe ,  Joo-Han Kim

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/14692

摘要： A method of manufacturing a thin film transistor array panel is provided, The method includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming a data line and a drain electrode on the semiconductor layer; depositing a passivation layer on the data line and the drain electrode; forming a photoresist including a first portion and a second portion thinner than the first portion on the passivation layer; etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode at least in part; removing the second portion of the photoresist; depositing a conductive film; and removing the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法。该方法包括：在基板上形成栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在半导体层上形成数据线和漏电极; 在数据线和漏电极上沉积钝化层; 在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂; 使用所述光致抗蚀剂作为掩模蚀刻所述钝化层，以至少部分地暴露所述漏电极的一部分; 去除光致抗蚀剂的第二部分; 沉积导电膜; 并且去除光致抗蚀剂以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US07405425B2

公开(公告)日：2008-07-29

申请号：US11232306

申请日：2005-09-20

申请人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L29/04

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

摘要翻译： 薄膜晶体管包括衬底上的栅电极，衬底上的栅极绝缘层，沟道图案，源电极和漏电极。 沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。 源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案，源图案和第一封盖图案。 漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案，漏极图案和第二封盖图案。 第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓，以防止源极和漏极的暴露，从而改善薄膜晶体管的特性。

公开(公告)号：US20060160282A1

公开(公告)日：2006-07-20

申请号：US11336087

申请日：2006-01-20

申请人： Jang-Soo Kim ,  Soo-Jin Kim ,  Kyoung-Tai Han ,  Hee-Hwan Choe ,  Joo-Han Kim

发明人： Jang-Soo Kim ,  Soo-Jin Kim ,  Kyoung-Tai Han ,  Hee-Hwan Choe ,  Joo-Han Kim

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L27/1288 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/14692

摘要： A method of manufacturing a thin film transistor array panel is provided, The method includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming a data line and a drain electrode on the semiconductor layer; depositing a passivation layer on the data line and the drain electrode; forming a photoresist including a first portion and a second portion thinner than the first portion on the passivation layer; etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode at least in part; removing the second portion of the photoresist; depositing a conductive film; and removing the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

公开(公告)号：US20100140626A1

公开(公告)日：2010-06-10

申请号：US12704503

申请日：2010-02-11

申请人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

发明人： Sang-Gab Kim ,  Min-Seok Oh ,  Hong-Kee Chin ,  Jeong-Min Park ,  Shi-Yul Kim ,  Hee-Hwan Choe

IPC分类号： H01L27/12

CPC分类号： H01L29/458 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1288

摘要： A method for manufacturing a TFT array panel including forming a gate line having a gate electrode on a insulating layer, a gate insulating layer on the gate line, a semiconductor on the gate insulating layer, an ohmic contact on the semiconductor, a data line having a source electrode and a drain electrode apart form the source electrode on the ohmic contact, a passivation layer having a contact hole to expose the drain electrode, and a pixel electrode connected to the drain electrode through the contact hole. The drain electrode and the source electrode are formed by a photolithography using a negative photoresist pattern. The negative photoresist pattern includes a first portion having a first thickness corresponding to a channel area, a second portion having a second thickness corresponding to a data line area, and a third portion having a third thickness corresponding to another area.

摘要翻译： 一种TFT阵列板的制造方法，包括在绝缘层上形成具有栅电极的栅极线，栅极线上的栅极绝缘层，栅极绝缘层上的半导体，半导体上的欧姆接触，数据线， 源电极和漏电极分开形成欧姆接触上的源电极，具有露出漏电极的接触孔的钝化层和通过接触孔连接到漏电极的像素电极。 漏电极和源电极通过使用负光致抗蚀剂图案的光刻形成。 负型光致抗蚀剂图案包括具有对应于沟道区域的第一厚度的第一部分，具有对应于数据线区域的第二厚度的第二部分和具有对应于另一区域的第三厚度的第三部分。

公开(公告)号：US20100047946A1

公开(公告)日：2010-02-25

申请号：US12609568

申请日：2009-10-30

申请人： Sang-Gab Kim ,  Sung-Chul Kang ,  Ho-Min Kang ,  In-Ho Song ,  Hee-Hwan Choe

发明人： Sang-Gab Kim ,  Sung-Chul Kang ,  Ho-Min Kang ,  In-Ho Song ,  Hee-Hwan Choe

IPC分类号： H01L21/28

CPC分类号： H01L27/1259 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262

摘要： A method of manufacturing a thin film array panel is provided, which includes: forming a gate line formed on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode disposed at least on the ohmic contact layer, forming an oxide on the data line; etching the ohmic contact layer using the data line and the drain electrode as an etch mask; and forming a pixel electrode connected to the drain electrode.

摘要翻译： 提供一种制造薄膜阵列面板的方法，其包括：形成在基底上的栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在所述半导体层上形成欧姆接触层; 形成至少设置在所述欧姆接触层上的数据线和漏电极，在所述数据线上形成氧化物; 使用数据线和漏电极作为蚀刻掩模蚀刻欧姆接触层; 以及形成连接到所述漏电极的像素电极。

公开(公告)号：US07588972B2

公开(公告)日：2009-09-15

申请号：US12146763

申请日：2008-06-26

申请人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

发明人： Sang-Gab Kim ,  Shi-Yul Kim ,  Hong-Sick Park ,  Hee-Hwan Choe ,  Hong-Kee Chin ,  Min-Seok Oh

IPC分类号： H01L21/00

CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the substrate, a channel pattern, a source electrode and a drain electrode. The channel pattern includes a semiconductor pattern formed on the gate electrode and overlaying the gate electrode as well as first and second conductive adhesive patterns formed on the semiconductor pattern and spaced apart from each other. The source electrode includes a first barrier pattern, a source pattern and a first capping pattern sequentially formed on the first conductive adhesive pattern. The drain electrode includes a second barrier pattern, a drain pattern and a second capping pattern sequentially formed on the second conductive adhesive pattern. Etched portions of the first and second conductive adhesive patterns have a substantially vertical profile to prevent the exposure of the source and drain electrodes, thereby improving the characteristics of the thin film transistor.

摘要翻译： 薄膜晶体管包括衬底上的栅电极，衬底上的栅极绝缘层，沟道图案，源电极和漏电极。 沟道图案包括形成在栅电极上并覆盖栅电极的半导体图案以及形成在半导体图案上并彼此间隔开的第一和第二导电粘合剂图案。 源电极包括顺序地形成在第一导电粘合剂图案上的第一阻挡图案，源图案和第一封盖图案。 漏电极包括顺序地形成在第二导电粘合剂图案上的第二阻挡图案，漏极图案和第二封盖图案。 第一和第二导电粘合剂图案的蚀刻部分具有基本垂直的轮廓，以防止源极和漏极的暴露，从而改善薄膜晶体管的特性。

公开(公告)号：US07172913B2

公开(公告)日：2007-02-06

申请号：US11082967

申请日：2005-03-18

申请人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

发明人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。