公开(公告)号：US06870928B1

公开(公告)日：2005-03-22

申请号：US09866525

申请日：2001-05-25

申请人： Cormac S. Conroy ,  Samuel W. Sheng ,  Ara Bicakci ,  John DeCelles ,  Sang-Soo Lee

发明人： Cormac S. Conroy ,  Samuel W. Sheng ,  Ara Bicakci ,  John DeCelles ,  Sang-Soo Lee

IPC分类号： H04L25/02 ,  H04L27/00 ,  H04M1/738 ,  H04M11/06 ,  H04M1/00

CPC分类号： H04L27/0002 ,  H04L25/0266 ,  H04M1/738 ,  H04M11/062

摘要： A line interface couples signals between a data transceiver and a transmission line having a load impedance Z. The line interface includes a transformer, a driver circuit for supplying a transmit signal from the data transceiver to the transformer, and a receiver circuit for receiving a receive signal from the transformer. The transformer includes a first port coupled to the transmission line, a second port coupled to the driver circuit, a third port coupled to the receiver circuit, a first winding part having a turns ratio of 1: n, where n>1, for coupling the transmit signal from the second port to the first port, and a second winding part having a turns ratio of 1: m, where m

摘要翻译： 线路接口在数据收发器和具有负载阻抗Z的传输线之间耦合信号。线路接口包括变压器，用于从数据收发器向变压器提供发送信号的驱动器电路，以及用于接收接收器的接收器电路 来自变压器的信号。 变压器包括耦合到传输线的第一端口，耦合到驱动器电路的第二端口，耦合到接收器电路的第三端口，具有匝数比为1：n的第一绕组部件，其中n> 1，用于耦合 从第二端口到第一端口的发送信号和匝数比为1：m的第二绕组部分，其中m

公开(公告)号：US07020277B1

公开(公告)日：2006-03-28

申请号：US10011153

申请日：2001-12-05

申请人： Sang-Soo Lee ,  Samuel W. Sheng ,  Cormac S. Conroy

发明人： Sang-Soo Lee ,  Samuel W. Sheng ,  Cormac S. Conroy

IPC分类号： H04B1/52

CPC分类号： H04L25/0266

摘要： A line interface couples a data transceiver to a transmission line via a transformer, the data transceiver transmitting signals in a first frequency range and receiving signals in a second frequency range. The line interface includes an input port for receiving an input signal voltage from an analog front end (AFE) chip, an output port, a line driver for amplifying the input signal voltage and supplying a transmit signal to the output port, a line port for sending the transmit signal and receiving a receive signal, termination resistors coupled between the output port and the line port, a receive signal port for supplying the receive signal to the AFE chip, a receive amplifier formed on the AFE chip coupled to the receive signal port, and a bridge network resistively coupling the line port and the output port to the receive signal port, the bridge network having a low-pass filter characteristic.

摘要翻译： 线路接口通过变压器将数据收发器耦合到传输线，数据收发器在第一频率范围内传输信号并在第二频率范围内接收信号。 线路接口包括用于从模拟前端（AFE）芯片接收输入信号电压的输入端口，输出端口，用于放大输入信号电压并向输出端口提供发送信号的线路驱动器，用于 发送发送信号并接收接收信号，耦合在输出端口和线路端口之间的终端电阻器，用于将接收信号提供给AFE芯片的接收信号端口，耦合到接收信号端口的AFE芯片上形成的接收放大器 ，桥接网络将线路端口和输出端口电阻地耦合到接收信号端口，桥接网络具有低通滤波器特性。

公开(公告)号：US06215431B1

公开(公告)日：2001-04-10

申请号：US09323670

申请日：1999-06-01

申请人： Samuel W. Sheng ,  Cormac S. Conroy

发明人： Samuel W. Sheng ,  Cormac S. Conroy

IPC分类号： H03M100

CPC分类号： H03M1/0631 ,  H03H19/004 ,  H03M1/0614 ,  H03M1/66

摘要： A reconstruction filter is described. An input is configured to receive an output signal from a digital to analog converter. An input sampling circuit is operative to store a sample of the output signal from the digital to analog converter. An input pulse generating switch that generates a pulse, the energy of the pulse being determined by the sample of the output signal from the digital to analog converter. An amplifier receives the pulse at an amplifier input and provides an output signal at an amplifier output so that an output signal is produced that reduces distortion caused by imperfections in digital to analog converter.

摘要翻译： 描述重构滤波器。 输入被配置为从数模转换器接收输出信号。 输入采样电路用于存储来自数模转换器的输出信号的采样。 产生脉冲的输入脉冲发生开关，脉冲的能量由来自数模转换器的输出信号的样本确定。 放大器在放大器输入端接收脉冲，并在放大器输出端提供输出信号，从而产生输出信号，减少由数模转换器中的缺陷引起的失真。

公开(公告)号：US06459684B1

公开(公告)日：2002-10-01

申请号：US09250426

申请日：1999-02-16

申请人： Cormac S. Conroy ,  Samuel W. Sheng ,  Gregory T. Uehara

发明人： Cormac S. Conroy ,  Samuel W. Sheng ,  Gregory T. Uehara

IPC分类号： H04B320

CPC分类号： H04L5/023

摘要： An ADSL central office transmission system for transmitting downstream DMT signals to a plurality of remote ADSL transceiver is disclosed. The system includes a DMT digital signal transceiver that generates a time division multiplexed digital signal that includes a plurality of DMT signals to be sent on a plurality of ADSL lines. A digital to analog converter converts the time division multiplexed digital signal into a time division multiplexed analog signal that includes a plurality of analog DMT signals. The analog to digital converter has an output that outputs the time division multiplexed analog signal. A switch selectively connects the output of the digital to analog converter to each of a plurality of transmitters. The transmitters are configured to drive the plurality of ADSL lines. Thus, the plurality ADSL lines are driven by the plurality of analog DMT signals.

摘要翻译： 公开了一种用于将下行DMT信号发送到多个远程ADSL收发器的ADSL中心局传输系统。 该系统包括DMT数字信号收发器，其产生包括要在多条ADSL线路上发送的多个DMT信号的时分复用数字信号。 数模转换器将时分多路复用数字信号转换成包括多个模拟DMT信号的时分复用模拟信号。 模数转换器具有输出时分复用的模拟信号的输出。 开关选择性地将数模转换器的输出连接到多个发射器中的每一个。 发射机被配置为驱动多条ADSL线路。 因此，多个ADSL线由多个模拟DMT信号驱动。

公开(公告)号：US07821362B2

公开(公告)日：2010-10-26

申请号：US12365708

申请日：2009-02-04

申请人： Samuel W. Sheng ,  Michael Khitrov

发明人： Samuel W. Sheng ,  Michael Khitrov

IPC分类号： H03J3/04 ,  H03J5/02 ,  H04B1/18

CPC分类号： H03J1/005 ,  H03J3/08 ,  H03J2200/08 ,  H04B1/18

摘要： In a signal communication device, a frequency-selective filter has at least one component that is biased by a control signal to establish a center frequency of the frequency-selective filter. A closed-loop bias generator is provided to generate the control signal and to adjust the control signal based, at least in part, on a comparison of the control signal and a reference signal.

摘要翻译： 在信号通信装置中，频率选择滤波器具有被控制信号偏置的至少一个分量，以建立频率选择滤波器的中心频率。 提供闭环偏置发生器来产生控制信号并且至少部分地基于控制信号和参考信号的比较来调节控制信号。

公开(公告)号：US07088979B1

公开(公告)日：2006-08-08

申请号：US09880291

申请日：2001-06-13

申请人： Ravindra U. Shenoy ,  Samuel W. Sheng ,  Lapoe E. Lynn

发明人： Ravindra U. Shenoy ,  Samuel W. Sheng ,  Lapoe E. Lynn

IPC分类号： H04B1/26

CPC分类号： H04B1/28

摘要： An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an upconverted signal in response to an input signal and a first oscillation signal. The second circuit may be configured to generate a downconverted signal in response to the upconverted signal and as second oscillation signal. The third circuit may be configured to generate an output signal in response to the downconverted signal and a third oscillation signal derived from the second oscillation signal. The upconverting and downconverting may filter undesired channels from the output signal.

摘要翻译： 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为响应于输入信号和第一振荡信号而产生上变频信号。 第二电路可以被配置为响应于上变频信号和第二振荡信号而产生下变频信号。 第三电路可以被配置为响应于下变频信号和从第二振荡信号导出的第三振荡信号来产生输出信号。 上变频和下变频可能会从输出信号中滤除不需要的通道。

公开(公告)号：US06771111B2

公开(公告)日：2004-08-03

申请号：US10341963

申请日：2002-01-13

申请人： Samuel W. Sheng ,  Ivan C. Eng

发明人： Samuel W. Sheng ,  Ivan C. Eng

IPC分类号： G06F7556

CPC分类号： G06G7/24

摘要： A precision analog exponentiation circuit includes a precision analog exponentiation circuit includes a first transistor coupled to a reference current for generating a voltage at the first transistor, a second transistor coupled to the first transistor for generating an output current, a variable current source coupled to the first transistor and the second transistor for generating a sum of the reference current and the output current in response to a feedback signal, and a feedback amplifier coupled to the first transistor for generating the feedback signal wherein the variable current source maintains the voltage at the first transistor substantially equal to a reference voltage so that the output current is substantially equal to an exponential function of a control voltage coupled to the first transistor and the second transistor.

摘要翻译： 精密模拟乘法电路包括精密模拟乘法电路，其包括耦合到参考电流的第一晶体管，用于在第一晶体管处产生电压，耦合到第一晶体管的第二晶体管，用于产生输出电流;耦合到第一晶体管的可变电流源 第一晶体管和第二晶体管，用于响应于反馈信号产生参考电流和输出电流之和，以及耦合到第一晶体管的反馈放大器，用于产生反馈信号，其中可变电流源保持第一 晶体管基本上等于参考电压，使得输出电流基本上等于耦合到第一晶体管和第二晶体管的控制电压的指数函数。

公开(公告)号：US06750726B1

公开(公告)日：2004-06-15

申请号：US10301099

申请日：2002-11-20

申请人： Chih-Jen Hung ,  Ravindra Shenoy ,  Samuel W. Sheng

发明人： Chih-Jen Hung ,  Ravindra Shenoy ,  Samuel W. Sheng

IPC分类号： H03B508

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/124 ,  H03B2202/027

摘要： An oscillator circuit includes an electrical load, a first metal oxide semiconductor (MOS) devise, a second MOS device, and a negative feedback circuit. The electrical load is coupled between a first node and a second node. The first MOS device is coupled between the first node and a third node, and controls a first current flowing from the first node to the third node. The second MOS device is coupled between the second node and a fourth node, and controls a second current flowing from the second node to the fourth node. A positive feedback circuit is formed with the first and second MOS devices. The positive feedback circuit has inputs from the first and second nodes and outputs to the first and second MOS devices. The negative feedback circuit has inputs from the third and fourth nodes and outs to the first and second MOS devices.

摘要翻译： 振荡电路包括电负载，第一金属氧化物半导体（MOS）器件，第二MOS器件和负反馈电路。 电负载耦合在第一节点和第二节点之间。 第一MOS器件耦合在第一节点和第三节点之间，并且控制从第一节点流向第三节点的第一电流。 第二MOS器件耦合在第二节点和第四节点之间，并且控制从第二节点流向第四节点的第二电流。 正反馈电路与第一和第二MOS器件形成。 正反馈电路具有来自第一和第二节点的输入，并输出到第一和第二MOS器件。 负反馈电路具有来自第三和第四节点的输入，并且输出到第一和第二MOS器件。

公开(公告)号：US06501409B1

公开(公告)日：2002-12-31

申请号：US09881570

申请日：2001-06-13

申请人： Lapoe Lynn ,  Samuel W. Sheng ,  Chih-Jen Hung

发明人： Lapoe Lynn ,  Samuel W. Sheng ,  Chih-Jen Hung

IPC分类号： H03M166

CPC分类号： H03M1/804

摘要： A circuit includes a switched-capacitor array for converting a digital signal into a corresponding amount of electric charge, a switching circuit, and a continuous-time reconstruction filter circuit. The switched-capacitor array includes a plurality of capacitors and a summing node to which the plurality of capacitors are connected. The switching circuit is coupled between the summing node and the continuous-time reconstruction filter circuit, and supplies a pulsed current signal to the continuous-time reconstruction filter circuit. The circuit may further include a gain stage coupled between the summing node and the switching circuit, for controlling a gain of the pulsed current signal. The gain stage may include a coupling capacitor. A digital signal is supplied to the switched capacitor array and converted into a corresponding amount of electric charge. The electric charge is supplied as a pulsed current signal to the continuous-time reconstruction filter circuit without converting into a voltage signal.

摘要翻译： 电路包括用于将数字信号转换成相应量的电荷的开关电容器阵列，开关电路和连续时间重构滤波器电路。 开关电容器阵列包括多个电容器和多个电容器连接的求和节点。 开关电路耦合在求和节点和连续时间重建滤波器电路之间，并将脉冲电流信号提供给连续时间重构滤波器电路。 电路还可以包括耦合在求和节点和开关电路之间的增益级，用于控制脉冲电流信号的增益。 增益级可以包括耦合电容器。 数字信号被提供给开关电容器阵列并转换成相应的电荷量。 将电荷作为脉冲电流信号提供给连续时间重构滤波器电路，而不转换成电压信号。

公开(公告)号：US07054606B1

公开(公告)日：2006-05-30

申请号：US09960560

申请日：2001-09-21

申请人： Samuel W. Sheng ,  Lapoe E. Lynn ,  Ivan C-Y Eng

发明人： Samuel W. Sheng ,  Lapoe E. Lynn ,  Ivan C-Y Eng

IPC分类号： H04Q7/20

CPC分类号： H03H11/1291

摘要： An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to filter an analog input signal in an analog domain in response to one or more control signals. The second circuit may be configured to convert the analog input signal to a digital signal. The third circuit may be configured to generate the control signals in response to the digital signal. The third circuit may also be configured to control skewing of the analog input signal within the first circuit to partially compensate for frequency dependent effects associated with a transmission medium.

摘要翻译： 一种包括第一电路，第二电路和第三电路的装置。 第一电路可以被配置为响应于一个或多个控制信号来对模拟域中的模拟输入信号进行滤波。 第二电路可以被配置为将模拟输入信号转换成数字信号。 第三电路可以被配置为响应于数字信号产生控制信号。 第三电路还可以被配置为控制第一电路内的模拟输入信号的偏斜以部分地补偿与传输介质相关联的频率相关效应。