Semiconductor device with surface and deep guard rings

    公开(公告)号:US12205984B2

    公开(公告)日:2025-01-21

    申请号:US17829791

    申请日:2022-06-01

    Abstract: A semiconductor device includes a semiconductor substrate, a top electrode in contact with a top surface of the semiconductor substrate, a bottom electrode in contact with a bottom surface of the semiconductor substrate, and an oxide film in contact with the top surface of the semiconductor substrate. The semiconductor substrate includes an element region and an outer peripheral region. The element region is a region where the top electrode is in contact with the top surface of the semiconductor substrate. The outer peripheral region is a region where the oxide film is in contact with the top surface of the semiconductor substrate, and is located between the element region and an outer peripheral end surface of the semiconductor substrate. The element region includes a semiconductor element connected between the top electrode and the bottom electrode. The outer peripheral region includes surface high-voltage-breakdown regions, deep high-voltage-breakdown regions, and a drift region.

    Switching device
    3.
    发明授权

    公开(公告)号:US10170470B2

    公开(公告)日:2019-01-01

    申请号:US15684057

    申请日:2017-08-23

    Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.

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