公开(公告)号：US10770579B2

公开(公告)日：2020-09-08

申请号：US15816697

申请日：2017-11-17

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Hidefumi Takaya ,  Yasushi Urakami ,  Yukihiko Watanabe

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417

Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.

公开(公告)号：US09825123B2

公开(公告)日：2017-11-21

申请号：US14975961

申请日：2015-12-21

Applicant: Toyota Jidosha Kabushiki Kaisha ,  Denso Corporation

Inventor： Tatsuji Nagaoka ,  Hiroki Miyake ,  Yukihiko Watanabe ,  Sachiko Aoi ,  Atsuya Akiba

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/872 ,  H01L29/66

CPC classification number: H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/66143 ,  H01L29/872

Abstract: A Schottky barrier diode provided herein includes: a semiconductor substrate; and an anode electrode being in contact with the semiconductor substrate. The semiconductor substrate includes: p-type contact regions being in contact with the anode electrode; and an n-type drift region being in contact with the anode electrode by Schottky contact in a range where the p-type contact regions are not provided The p-type contact regions includes: a plurality of circular regions located so that the circular regions are arranged at intervals between an outer side and an inner side at a contact surface between the semiconductor substrate and the anode electrode; and an internal region located in an inner portion of the circular region located on an innermost side at the contact surface and connected to the circular region located on the innermost side at the contact surface.

公开(公告)号：US09793376B2

公开(公告)日：2017-10-17

申请号：US14415752

申请日：2013-08-06

Applicant: DENSO CORPORATION ,  Jun Morimoto

Inventor： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Jun Morimoto ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC: H01L31/0312 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L21/306 ,  H01L21/04 ,  H01L21/28 ,  H01L29/04 ,  H01L29/10

CPC classification number: H01L29/66734 ,  H01L21/049 ,  H01L21/28158 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813

Abstract: In a method of manufacturing a silicon carbide semiconductor device including a vertical switching element having a trench gate structure, with the use of a substrate having an off angle with respect to a (0001) plane or a (000-1) plane, a trench is formed from a surface of a source region to a depth reaching a drift layer through a base region so that a side wall surface of the trench faces a (11-20) plane or a (1-100) plane, and a gate oxide film is formed without performing sacrificial oxidation after formation of the trench.

公开(公告)号：US09660046B2

公开(公告)日：2017-05-23

申请号：US14438824

申请日：2014-01-09

Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Sachiko Aoi ,  Yukihiko Watanabe ,  Katsumi Suzuki ,  Shoji Mizuno

IPC: H01L21/332 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739 ,  H01L29/16 ,  H01L29/417 ,  H01L29/08 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/66348 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method of manufacturing a semiconductor device includes: forming a first trench in a first area of a drift layer that has a surface including the first area and a second area; growing a crystal of a p-type base layer on a surface of the drift layer after forming the first trench; and growing a crystal of an n-type source layer on a surface of the base layer. Material of the drift layer, the base layer, and the source layer are a wide-gap semiconductor.

公开(公告)号：US09391190B2

公开(公告)日：2016-07-12

申请号：US14299922

申请日：2014-06-09

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Yukihiko Watanabe ,  Sachiko Aoi ,  Hidefumi Takaya ,  Atsuya Akiba

IPC: H01L29/78 ,  H01L29/872 ,  H01L29/66 ,  H01L27/02 ,  H01L21/04 ,  H01L29/16

CPC classification number: H01L29/7806 ,  H01L21/049 ,  H01L21/0495 ,  H01L27/0255 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/872

Abstract: A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region.

Abstract translation: 结合肖特基二极管的FET具有能够自由调节形成肖特基二极管的区域与形成FET的区域的比例的结构。 利用长距离延伸的沟槽。 肖特基电极插入在沟槽的纵向上间断地出现的位置。 通过利用在SiC上形成的热氧化膜的生长速度较慢，并且在多晶硅上形成的热氧化膜的生长速度更快，可以获得在栅电极和肖特基电极之间形成绝缘膜的结构 在栅电极和源极区之间，栅电极与体区之间以及栅电极和漏区之间，并且在肖特基电极和漏极区之间不形成绝缘膜。

公开(公告)号：US20160181355A1

公开(公告)日：2016-06-23

申请号：US14975961

申请日：2015-12-21

Applicant: Toyota Jidosha Kabushiki Kaisha ,  Denso Corporation

Inventor： Tatsuji Nagaoka ,  Hiroki Miyake ,  Yukihiko Watanabe ,  Sachiko Aoi ,  Atsuya Akiba

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/16 ,  H01L29/872

CPC classification number: H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/66143 ,  H01L29/872

Abstract: A Schottky barrier diode provided herein includes: a semiconductor substrate; and an anode electrode being in contact with the semiconductor substrate. The semiconductor substrate includes: p-type contact regions being in contact with the anode electrode; and an n-type drift region being in contact with the anode electrode by Schottky contact in a range where the p-type contact regions are not provided The p-type contact regions includes: a plurality of circular regions located so that the circular regions are arranged at intervals between an outer side and an inner side at a contact surface between the semiconductor substrate and the anode electrode; and an internal region located in an inner portion of the circular region located on an innermost side at the contact surface and connected to the circular region located on the innermost side at the contact surface.

Abstract translation: 本文提供的肖特基势垒二极管包括：半导体衬底; 以及与半导体衬底接触的阳极电极。 半导体衬底包括：与阳极电极接触的p型接触区域; 以及在没有设置p型接触区域的范围内通过肖特基接触与阳极电极接触的n型漂移区域p型接触区域包括：多个圆形区域，其位于圆形区域 在所述半导体衬底和所述阳极电极之间的接触表面处间隔布置在所述外侧和内侧之间; 以及位于位于接触表面的最内侧的圆形区域的内部的内部区域，并且连接到位于接触表面最内侧的圆形区域。

公开(公告)号：US09911803B2

公开(公告)日：2018-03-06

申请号：US15023498

申请日：2014-09-22

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun Saito ,  Sachiko Aoi ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor substrate. The element region of the semiconductor substrate includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and a plurality of first floating regions, each the first floating regions having the first conductivity type. The termination region includes a second drift region having the second conductivity type, and a plurality of second floating regions, each of the second floating regions having the first conductivity type. The each of the second floating regions is surrounded by the second drift region. When a depth of a center of the first drift region is taken as a reference depth, at least one of the second floating regions is placed closer to the reference depth than each of the first floating regions.

公开(公告)号：US09647108B2

公开(公告)日：2017-05-09

申请号：US15025930

申请日：2014-09-15

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Naohiro Suzuki ,  Sachiko Aoi ,  Yukihiko Watanabe ,  Akitaka Soeno ,  Masaki Konishi

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer; a current dispersion layer; a base region; a source region; trenches; a gate insulation film; a gate electrode; a source electrode; a drain electrode; and a bottom layer. The current dispersion layer is arranged on the drift layer, and has a first conductive type with an impurity concentration higher than the drift layer. The bottom layer has a second conductive type, is arranged under the base region, covers a bottom of each trench including a corner portion of the bottom of the trench, and has a depth equal to or deeper than the current dispersion layer.

公开(公告)号：US09515160B2

公开(公告)日：2016-12-06

申请号：US15001726

申请日：2016-01-20

Applicant: DENSO CORPORATION ,  KAZUMI CHIDA

Inventor： Yuichi Takeuchi ,  Kazumi Chida ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/04 ,  H01L29/739 ,  H01L29/78 ,  H01L29/16 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/66068 ,  H01L21/02529 ,  H01L21/0455 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.

Abstract translation: 在制造SiC半导体器件的方法中，通过外延生长在沟槽中形成p型层，然后仅通过氢蚀刻留在沟槽的底部和端部，从而形成p型SiC层。 因此，可以不依赖于对角离子注入来形成p型SiC层。 由于不需要单独进行对角线离子注入，因此生产工艺由于转移到离子注入装置中而不太可能复杂，因此制造成本降低。 由于由于离子注入引起的缺陷而没有损坏，因此可以减少漏极泄漏并且可靠地限制p型SiC层残留在沟槽的侧表面上。

公开(公告)号：US09219142B2

公开(公告)日：2015-12-22

申请号：US14491332

申请日：2014-09-19

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun Saito ,  Sachiko Aoi ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a termination region. The element region includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and first floating regions having the first conductivity type. The termination region includes FLR regions, a second drift region and second floating regions. The FLR regions have the first conductivity type and surrounds the element region. The second drift region has the second conductivity type, makes contact with and surrounds the FLR regions. The second floating regions have the first conductivity type and is surrounded by the second drift region. The second floating regions surround the element region. At least one of the second floating regions is placed at an element region side relative to the closest one of the FLR regions to the element region.

Abstract translation: 半导体器件包括具有元件区域和端接区域的半导体衬底。 元件区域包括具有第一导电类型的第一主体区域，具有第二导电类型的第一漂移区域和具有第一导电类型的第一浮动区域。 终止区域包括FLR区域，第二漂移区域和第二浮动区域。 FLR区域具有第一导电类型并且围绕元件区域。 第二漂移区域具有第二导电类型，与FLR区域接触并围绕FLR区域。 第二浮动区域具有第一导电类型并被第二漂移区域围绕。 第二浮动区域围绕元件区域。 第二浮动区域中的至少一个相对于元件区域中最近的一个FLR区域放置在元件区域侧。