公开(公告)号：US07426656B2

公开(公告)日：2008-09-16

申请号：US11042548

申请日：2005-01-25

申请人： David L. Bernick ,  William F. Bruckert ,  David J. Garcia ,  Robert L. Jardine ,  James S. Klecka ,  Pankaj Mehra ,  James R. Smullen

发明人： David L. Bernick ,  William F. Bruckert ,  David J. Garcia ,  Robert L. Jardine ,  James S. Klecka ,  Pankaj Mehra ,  James R. Smullen

IPC分类号： G06F11/00

CPC分类号： G06F11/1683 ,  G06F9/3851 ,  G06F9/3861 ,  G06F11/1482 ,  G06F11/1645 ,  G06F11/1691

摘要： A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.

摘要翻译： 松散锁定非确定性处理器的方法和系统。 一些示例性实施例可以是基于处理器的方法，包括执行用户程序的容错副本，在执行非确定性执行的第一处理器中执行的用户程序的一个副本以及在第二处理器中执行的用户程序的副本 执行非确定性执行，其中在第一处理器和第二处理器中的执行不是按循环逐步锁定。

公开(公告)号：US07434098B2

公开(公告)日：2008-10-07

申请号：US11042981

申请日：2005-01-25

申请人： David L. Bernick ,  William F. Bruckert ,  David J. Garcia ,  Robert L. Jardine ,  Pankaj Mehra ,  James R. Smullen

发明人： David L. Bernick ,  William F. Bruckert ,  David J. Garcia ,  Robert L. Jardine ,  Pankaj Mehra ,  James R. Smullen

IPC分类号： G06F11/00

CPC分类号： G06F11/1658 ,  G06F9/52 ,  G06F11/1641 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/184 ,  G06F11/185 ,  G06F11/3404 ,  G06F11/3476 ,  G06F11/3495 ,  G06F11/3636 ,  G06F11/366 ,  G06F2201/88

摘要： Method and system of determining whether a user program has made a system level call and thus whether the user program is uncooperative with fault tolerant operation. Some exemplary embodiments may be a processor-based method comprising providing information from a first processor to a second processor (the information indicating that a user program executed on the first processor has not made a system level call in a predetermined amount of time), and determining by the first processor, using information from the second processor, whether a duplicate copy of the user program substantially simultaneously executed in the second processor has made a system level call in the predetermined amount of time.

摘要翻译： 确定用户程序是否进行了系统级别的调用以及用户程序是否不兼容容错操作的方法和系统。 一些示例性实施例可以是基于处理器的方法，包括从第一处理器向第二处理器提供信息（指示在第一处理器上执行的用户程序在预定时间量内没有进行系统级别调用的信息），以及 由第一处理器确定使用来自第二处理器的信息，在第二处理器中基本上同时执行的用户程序的副本是否在预定的时间量内进行了系统级的调用。

公开(公告)号：US07308605B2

公开(公告)日：2007-12-11

申请号：US10894825

申请日：2004-07-20

申请人： Robert L. Jardine ,  David L. Bernick ,  Thomas A. Heynemann ,  James R. Smullen

发明人： Robert L. Jardine ,  David L. Bernick ,  Thomas A. Heynemann ,  James R. Smullen

IPC分类号： G06F11/00

CPC分类号： G06F11/1666 ,  G06F11/1004 ,  G06F11/1633

摘要： In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is compared to detect a latent processing error in a first memory region. The latent processing error is resolved by copying data from a second memory region into the first memory region where the data maintained in the second memory region is determined to be identical to data maintained in at least a third memory region.

摘要翻译： 在潜在错误检测的实现中，扫描每个对应于冗余处理器系统的不同处理器元件的存储器区域作为错误数据维护的潜在处理错误。 将保存在存储器区域中的数据进行比较，以检测第一存储器区域中的潜在处理误差。 通过将数据从第二存储器区域复制到第一存储器区域中来解决潜在处理错误，其中保持在第二存储器区域中的数据被确定为与至少第三存储器区域中保持的数据相同。

公开(公告)号：US07764689B2

公开(公告)日：2010-07-27

申请号：US11229109

申请日：2005-09-16

申请人： David L. Bernick ,  Robert L. Jardine ,  Marcelo M. de Azevedo

发明人： David L. Bernick ,  Robert L. Jardine ,  Marcelo M. de Azevedo

IPC分类号： H04L12/28

CPC分类号： H04L45/34 ,  H04L45/02 ,  H04L45/24 ,  H04L45/72 ,  H04L47/50 ,  H04L47/56 ,  H04L47/562 ,  H04L47/568 ,  H04L47/623 ,  H04L47/6255

摘要： Techniques for routing data packets in a networked system. Specifically, a network system and methods of arbitrating data packets in a network system are provided. Switching devices are configured to receive one or more data packets, wherein each of the one or more data packets includes a respective source identification. The source identifications are compared to a source identification history mechanism, and the routing order of the data packets is determined based on the comparison.

摘要翻译： 在网络系统中路由数据包的技术。 具体地说，提供网络系统和网络系统中的数据分组仲裁方法。 交换设备被配置为接收一个或多个数据分组，其中所述一个或多个数据分组中的每一个包括相应的源标识。 将源标识与源识别历史机制进行比较，并且基于比较确定数据分组的路由顺序。

公开(公告)号：US09225632B2

公开(公告)日：2015-12-29

申请号：US11228657

申请日：2005-09-16

申请人： David L. Bernick ,  Curtis W. Landry

发明人： David L. Bernick ,  Curtis W. Landry

IPC分类号： H04L12/721 ,  H04L12/863 ,  H04L12/873 ,  H04L12/707 ,  H04L12/751

CPC分类号： H04L45/34 ,  H04L45/02 ,  H04L45/24 ,  H04L45/72 ,  H04L47/50 ,  H04L47/56 ,  H04L47/562 ,  H04L47/568 ,  H04L47/623 ,  H04L47/6255

摘要： Techniques for routing data packets in a networked system. Specifically, a network system and methods of arbitrating data packets in a network system are provided. Switching devices are configured to receive one or more data packets, wherein each of the one or more data packets is received at a respective input port each having a respective input port identification. The routing order of the data packets is determined based on the input port identification corresponding to the respective input port at which each of the data packets is received.

摘要翻译： 在网络系统中路由数据包的技术。 具体地说，提供网络系统和网络系统中的数据分组仲裁方法。 交换设备被配置为接收一个或多个数据分组，其中一个或多个数据分组中的每一个在相应的输入端口处被接收，每个输入端口具有相应的输入端口标识。 基于与接收每个数据分组的各个输入端口相对应的输入端口标识来确定数据分组的路由顺序。

公开(公告)号：US4821170A

公开(公告)日：1989-04-11

申请号：US40513

申请日：1987-04-17

申请人： David L. Bernick ,  Kenneth K. Chan ,  Wing M. Chan ,  Yie-Fong Dan ,  Duc M. Hoang ,  Zubair Hussain ,  Geoffrey I. Iswandhi ,  James E. Korpi ,  Martin W. Sanner ,  Jay A. Zwagerman ,  Steven G. Silverman ,  James E. Smith

发明人： David L. Bernick ,  Kenneth K. Chan ,  Wing M. Chan ,  Yie-Fong Dan ,  Duc M. Hoang ,  Zubair Hussain ,  Geoffrey I. Iswandhi ,  James E. Korpi ,  Martin W. Sanner ,  Jay A. Zwagerman ,  Steven G. Silverman ,  James E. Smith

IPC分类号： G06F11/18 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40 ,  G06F15/16

CPC分类号： G06F13/28 ,  G06F13/122 ,  G06F13/4022 ,  G06F11/10

摘要： In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.