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    Semiconductor devices having a convex active region and methods of forming the same
    1.
    发明申请
    Semiconductor devices having a convex active region and methods of forming the same 有权
    具有凸起的有源区的半导体器件及其形成方法

    公开(公告)号：US20080057644A1

    公开(公告)日：2008-03-06

    申请号：US11642198

    申请日：2006-12-20

    申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

    摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

    摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

    SEMICONDUCTOR DEVICES HAVING A CONVEX ACTIVE REGION
    2.
    发明申请
    SEMICONDUCTOR DEVICES HAVING A CONVEX ACTIVE REGION 审中-公开
    具有凸起活动区域的半导体器件

    公开(公告)号：US20090236651A1

    公开(公告)日：2009-09-24

    申请号：US12463545

    申请日：2009-05-11

    申请人： Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    发明人： Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    IPC分类号： H01L27/105 ,  H01L29/788

    CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

    摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

    摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

    Semiconductor devices having a convex active region and methods of forming the same
    3.
    发明授权
    Semiconductor devices having a convex active region and methods of forming the same 有权
    具有凸起的有源区的半导体器件及其形成方法

    公开(公告)号：US07544565B2

    公开(公告)日：2009-06-09

    申请号：US11642198

    申请日：2006-12-20

    申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

    摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

    摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

    Methods of forming a semiconductor device that allow patterns in different regions that have different pitches to be connected
    8.
    发明授权
    Methods of forming a semiconductor device that allow patterns in different regions that have different pitches to be connected 有权
    形成允许具有不同间距的不同区域中的图案被连接的半导体器件的方法

    公开(公告)号：US07419909B2

    公开(公告)日：2008-09-02

    申请号：US11647722

    申请日：2006-12-29

    申请人： Jin-Ho Kim ,  Jae-Kwan Park ,  Dong-Hwa Kwak ,  Su-Jin Ahn ,  Yoon-Moon Park ,  Jue-Hwang Sim ,  Jang-Ho Park ,  Sang-Yong Park

    发明人： Jin-Ho Kim ,  Jae-Kwan Park ,  Dong-Hwa Kwak ,  Su-Jin Ahn ,  Yoon-Moon Park ,  Jue-Hwang Sim ,  Jang-Ho Park ,  Sang-Yong Park

    IPC分类号： H01L21/302

    CPC分类号： H01L27/11568 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/105

    摘要： Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an etching mask.

    摘要翻译： 通过在半导体衬底上限定包括第一区域和第二区域的下层形成半导体器件中的图案，形成具有延伸到第一和第二区域的第一间距的第一图案，以第二间距形成第二图案 所述第二区域与所述第一图案交替布置，形成覆盖所述第一图案和所述第二图案的间隔绝缘层，并且包括与所述第一图案交替布置以与所述第二图案对应的间隙区域，形成与所述第二图案对应的第三图案 分别在间隙区域中蚀刻第一和第二图案之间以及第一和第三图案之间的空间绝缘层，使得空​​间绝缘层保留在第二图案和第三图案之间，并蚀刻下部 使用第一，第二和第三图案和第二个之间的剩余空间绝缘层 nd第三图案作为蚀刻掩模。