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    NAND-type non-volatile memory devices having a stacked structure and associated methods of forming and operating the same
    5.
    发明申请
    NAND-type non-volatile memory devices having a stacked structure and associated methods of forming and operating the same 失效
    具有堆叠结构的NAND型非易失性存储器件及其形成和操作的相关方法

    公开(公告)号：US20070165455A1

    公开(公告)日：2007-07-19

    申请号：US11637686

    申请日：2006-12-12

    申请人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    发明人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L29/788

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578

    摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

    摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。 在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。 在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。 第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。 外延接触插塞通过第一层间介电层与半导体衬底接触。 单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。 多个平行的第二字线布置在单晶半导体层上。 形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。 第二层间介电层设置在多个第二字线和单晶半导体层上。

    NAND-type non-volatile memory devices having a stacked structure
    6.
    发明授权
    NAND-type non-volatile memory devices having a stacked structure 失效
    具有堆叠结构的NAND型非易失性存储器件

    公开(公告)号：US07626228B2

    公开(公告)日：2009-12-01

    申请号：US11637686

    申请日：2006-12-12

    申请人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    发明人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    IPC分类号： H01L29/792 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578

    摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

    摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。 在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。 在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。 第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。 外延接触插塞通过第一层间介电层与半导体衬底接触。 单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。 多个平行的第二字线布置在单晶半导体层上。 形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。 第二层间介电层设置在多个第二字线和单晶半导体层上。

    I-AND II-TYPE CRYSTALS OF L-A-GLYCERYL PHOSPHORYL CHOLINE, AND METHOD FOR PREPARING SAME
    7.
    发明申请
    I-AND II-TYPE CRYSTALS OF L-A-GLYCERYL PHOSPHORYL CHOLINE, AND METHOD FOR PREPARING SAME 有权
    L-A-GLYCERYL PHOSPHORYL CHOLINE的I型和II型晶体及其制备方法

    公开(公告)号：US20130345464A1

    公开(公告)日：2013-12-26

    申请号：US14003276

    申请日：2012-02-22

    申请人： Min-Keun Oh ,  Ki-Nam Kim ,  Ki-Hyeong Seo ,  Dae-Gil Kwon

    发明人： Min-Keun Oh ,  Ki-Nam Kim ,  Ki-Hyeong Seo ,  Dae-Gil Kwon

    IPC分类号： C07F9/09

    CPC分类号： C07F9/091

    摘要： The present invention relates to I- and II-type crystals of L-α-glyceryl phosphoryl choline, and to a method for preparing same. More particularly, the present invention relates to noble I- and II-type anhydride crystals of L-α-glyceryl phosphoryl choline, which have a higher purity than conventional liquid L-α-glyceryl phosphoryl choline, and one advantage of which is that formulations and dosages of pharmaceuticals are easily modified, and another advantage of which is that the hygroscopicity of the crystals are much lower than that of conventional polymorphic crystals, providing excellent stability during storage. The present invention also relates to a method for preparing the I- and II-type crystals of L-α-glyceryl phosphoryl choline.

    摘要翻译： 本发明涉及L-α-甘油磷酰胆碱的I型和II型晶体及其制备方法。 更具体地，本发明涉及具有比常规液体L-α-甘油磷酰胆碱更高纯度的L-α-甘油磷酰胆碱的高级I型和II型酸酐晶体，其优点之一是制剂 并且药物的剂量容易改性，其另一个优点是结晶的吸湿性远低于常规多晶型晶体的吸湿性，在储存期间提供极好的稳定性。 本发明还涉及一种制备L-α-甘油磷酰胆碱的I型和II型晶体的方法。

    Semiconductor device and method of forming the same
    8.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US08026504B2

    公开(公告)日：2011-09-27

    申请号：US12379814

    申请日：2009-03-02

    申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    IPC分类号： H01L47/00

    CPC分类号： H01L27/24 ,  Y10S977/774

    摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

    摘要翻译： 提供半导体器件及其形成方法。 该方法包括制备半导体衬底。 可以在半导体衬底上依次形成绝缘层。 可以在绝缘层之间形成有源元件。 可以在绝缘层中形成公共节点以电连接到有源元件。 公共节点和有源元件可以二维重复地布置在半导体衬底上。

    Phase change memory device
    9.
    发明授权
    Phase change memory device 失效
    相变存储器件

    公开(公告)号：US07888667B2

    公开(公告)日：2011-02-15

    申请号：US12008125

    申请日：2008-01-09

    申请人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    发明人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    IPC分类号： H01L47/00 ,  H01L21/00 ,  G11C11/00

    CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1683 ,  Y10S438/90

    摘要： A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

    摘要翻译： 相变存储器件包括设置在基板上的模具层，加热电极，填充绝缘图案和相变材料图案。 加热电极设置在使基板穿过模具层的开口中。 加热电极形成为大致圆筒形，其侧壁共形地设置在开口的下内壁上。 填充绝缘图案填充由加热电极的侧壁围绕的空白区域。 相变材料图案设置在模具层上并向下延伸以填充开口的空的部分。 相变材料图案接触加热电极的侧壁的顶表面。

    Methods of Forming One Transistor DRAM Devices
    10.
    发明申请
    Methods of Forming One Transistor DRAM Devices 有权
    形成一个晶体管DRAM器件的方法

    公开(公告)号：US20100330752A1

    公开(公告)日：2010-12-30

    申请号：US12842703

    申请日：2010-07-23

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/322 ,  H01L21/336

    CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

    摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。