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1.发明公开公开(公告)号：US20240062809A1
公开(公告)日：2024-02-22
申请号：US18499634
申请日：2023-11-01
Inventor： Jin-Ho HAN , Byung-Jo KIM , Ju-Yeob KIM , Hye-Ji KIM , Joo-Hyun LEE , Seong-Min KIM
IPC: G11C11/4096 , G06F7/544 , G06N3/063 , G11C11/4093 , G11C11/54
CPC classification number: G11C11/4096 , G06F7/5443 , G06N3/063 , G11C11/4093 , G11C11/54
Abstract: Disclosed herein is an Artificial Intelligence (AI) processor. The AI processor includes multiple NVM AI cores for respectively performing basic unit operations required for a deep-learning operation based on data stored in NVM; SRAM for storing at least some of the results of the basic unit operations; and an AI core for performing an accumulation operation on the results of the basic unit operation.
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公开(公告)号：US20240211401A1
公开(公告)日：2024-06-27
申请号：US18522776
申请日：2023-11-29
Inventor： Jin-Ho HAN , Young-Su KWON
IPC: G06F12/0815 , G06F12/1027
CPC classification number: G06F12/0815 , G06F12/1027
Abstract: Disclosed herein are a method for supporting cache coherency based on virtual addresses for an artificial intelligence processor having large on-chip memory and an apparatus for the same. The method for supporting cache coherency according to an embodiment of the present disclosure includes, by an artificial intelligence processor including multiple processor cores and multiple caches, setting external memory address areas which do not overlap each other for respective multiple caches; and providing virtual addresses with which the multiple processor cores access the multiple caches.
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3.发明公开公开(公告)号：US20230259581A1
公开(公告)日：2023-08-17
申请号：US18109690
申请日：2023-02-14
Inventor： Won JEON , Young-Su KWON , Ju-Yeob KIM , Hyun-Mi KIM , Hye-Ji KIM , Chun-Gi LYUH , Mi-Young LEE , Jae-Hoon CHUNG , Yong-Cheol CHO , Jin-Ho HAN
Abstract: Disclosed herein is a method for outer-product-based matrix multiplication for a floating-point data type includes receiving first floating-point data and second floating-point data and performing matrix multiplication on the first floating-point data and the second floating-point data, and the result value of the matrix multiplication is calculated based on the suboperation result values of floating-point units.
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公开(公告)号：US20150293827A1
公开(公告)日：2015-10-15
申请号：US14677297
申请日：2015-04-02
Inventor： Jin-Ho HAN , Young-Su KWON , Kyung-Jin BYUN
IPC: G06F11/263 , G06F11/22
CPC classification number: G06F11/2215
Abstract: The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.
Abstract translation: 本发明涉及一种用于计算错误率的装置，包括：第一电路接口，连接到第一子电路，接收数据并通过预定的计算过程计算输出数据; 第二电路接口，并连接到接收相同数据的第一测试电路，其被输入到第一子电路，并通过预定的计算过程来计算输出数据; 向第一测试电路注入错误的误差注入部分; 将所述第一子电路的输出数据与所述第一测试电路的输出数据进行比较的误差检测部; 以及错误率计算部分通过对比结果的统计处理来计算第一子电路的输入节点误差概率。 与全电路的直接模拟相比，本发明的计算误差率的装置和方法能够缩短获得误差概率所需的时间。
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公开(公告)号：US20140344623A1
公开(公告)日：2014-11-20
申请号：US14255481
申请日：2014-04-17
Inventor： Jin-Ho HAN
IPC: G06F11/07
CPC classification number: G06F11/0724 , G06F11/0721 , G06F11/0751
Abstract: An apparatus and method for detecting the fault of a processor are disclosed. The apparatus includes a fetch fault control unit, a decoding fault control unit, and an execution fault control unit. The fetch fault control unit detects the fault of each of fetch units of a plurality of processor cores connected to memory. The decoding fault control unit detects the fault of each of decoding units of the plurality of processor cores connected to the memory. The execution fault control unit detects the fault of each of execution units of the plurality of processor cores connected to the memory, executes the same instruction in the plurality of processor cores, determines a processor core where a fault has occurred, and provides notification of the determined processor to the fetch fault control unit and the decoding fault control unit.
Abstract translation: 公开了一种用于检测处理器故障的装置和方法。 该装置包括取出故障控制单元，解码故障控制单元和执行故障控制单元。 获取故障控制单元检测连接到存储器的多个处理器核心中的每个提取单元的故障。 解码故障控制单元检测连接到存储器的多个处理器核心中的每个解码单元的故障。 执行故障控制单元检测连接到存储器的多个处理器核心中的每个执行单元的故障，在多个处理器核心中执行相同的指令，确定出现故障的处理器核心，并且提供 确定处理器到获取故障控制单元和解码故障控制单元。
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Patent Agency Ranking
公开(公告)号：US20220171708A1
公开(公告)日：2022-06-02
申请号：US17536573
申请日：2021-11-29
Inventor： Joo-Hyun LEE , Young-Su KWON , Jin-Ho HAN
IPC: G06F12/084 , G06F8/41 , G06F8/60
Abstract: Disclosed herein is a heterogeneous system based on unified virtual memory. The heterogeneous system based on unified virtual memory may include a host for compiling a kernel program, which is source code of a user application, in a binary form and delivering the compiled kernel program to a heterogenous system architecture device, the heterogenous system architecture device for processing operation of the kernel program delivered from the host in parallel using two or more different types of processing elements, and unified virtual memory shared between the host and the heterogenous system architecture device.
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公开(公告)号：US20240176590A1
公开(公告)日：2024-05-30
申请号：US18522797
申请日：2023-11-29
Inventor： Jin-Ho HAN
CPC classification number: G06F7/5443 , G06F5/01 , G06F7/483
Abstract: An embodiment of the present disclosure may provide a multiply-accumulate operation method performed by a multiply-accumulate operation apparatus, the multiply-accumulate operation method including accumulating, by an accumulation register, a value within a preset bit value of a mantissa bitwidth in a result of an addition operation of a shifted first mantissa value and a shifted second mantissa value, determining, by an overflow counter, an overflow count based on an overflow value by which the result of the addition operation of the shifted first mantissa value and the shifted second mantissa value exceeds the preset bit value of the mantissa bitwidth, performing normalization and rounding based on the value accumulated in the accumulation register and the overflow count, and updating, by an exponent updater, the exponent using a normalized and rounded value.
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公开(公告)号：US20230115549A1
公开(公告)日：2023-04-13
申请号：US17903112
申请日：2022-09-06
Inventor： Yi-Gyeong KIM , Young-deuk JEON , Young-Su KWON , Jin-Ho HAN
Abstract: Disclosed herein is an apparatus for receiving a strobe signal. The apparatus may include an amplifier for amplifying a strobe signal input thereto, an offset generator for controlling the setting of a threshold for detecting a preamble signal by generating an offset for the amplifier, and a preamble detector for detecting a first preamble signal occurring at a point at which the amplified strobe signal is equal to or greater than the threshold and turning off the offset generator when the first preamble signal is detected.
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公开(公告)号：US20220180162A1
公开(公告)日：2022-06-09
申请号：US17544224
申请日：2021-12-07
Inventor： Jin-Ho HAN , Young-Su KWON , Mi-Young LEE , Joo-Hyun LEE , Yong-Cheol CHO
IPC: G06N3/063
Abstract: Disclosed herein is an AI accelerator. The AI accelerator includes processors, each performing a deep-learning operation using multiple threads; and a cache memory including an L0 instruction cache for providing instructions to the processors and an L1 cache mapped to the multiple areas of mapped memory.
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公开(公告)号：US20160110250A1
公开(公告)日：2016-04-21
申请号：US14858448
申请日：2015-09-18
Inventor： Jin-Ho HAN , Young-Su KWON
CPC classification number: G06F11/1064 , G06F12/0895 , G06F2212/1032
Abstract: The exemplary embodiments of the invention relates to fault tolerance of a cache memory which recovers an error occurred in the cache memory or reports an error. A cache memory may include a first layer cache configured to store data requested from a processor, together with a tag related to the data and parity check bits for detecting data error and tag error; a second layer cache configured to store data requested from the first layer cache, together with parity check bits and an error correction code(ECC) bit for detecting data error and tag error; and a fault tolerance unit configured to generate an error signal indicating whether the data error or tag error occurred in at least one of the first layer cache and the second layer cache is recoverable.
Abstract translation: 本发明的示例性实施例涉及高速缓冲存储器的容错，其恢复在高速缓冲存储器中发生的错误或报告错误。 高速缓冲存储器可以包括配置成存储从处理器请求的数据的第一层缓存以及与数据有关的标签和用于检测数据错误和标签错误的奇偶校验位; 第二层缓存，配置为存储从第一层高速缓存请求的数据，以及奇偶校验位和用于检测数据错误和标签错误的纠错码（ECC）位; 以及容错单元，被配置为生成指示在所述第一层高速缓冲存储器和所述第二层高速缓冲存储器中的至少一个中发生的数据错误或标签错误是否可恢复的错误信号。
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