公开(公告)号：US10326647B2

公开(公告)日：2019-06-18

申请号：US15644434

申请日：2017-07-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kyuseung Han ,  Woojoo Lee ,  Jae-Jin Lee ,  Sung Weon Kang

IPC: H01L29/78 ,  H03K17/14 ,  H03K19/00 ,  H04L12/24 ,  H04L12/26 ,  H03K19/003 ,  H04L12/933

Abstract: Provided is a network-on-chip (NoC). The NoC includes a plurality of routers configured to receive power through each corresponding power gating switch, and a controller configured to control a power gating switch of each of the plurality of routers based on temperature information provided from each of the plurality of routers and control a driving clock of the plurality of routers. The controller controls the power gating switch to turn off at least one first router by referring to the temperature information and over-scale a clock frequency of at least one turned-on second router.

公开(公告)号：US12267631B2

公开(公告)日：2025-04-01

申请号：US17399603

申请日：2021-08-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sukho Lee ,  Sang Pil Kim ,  Young Hwan Bae ,  Jae-Jin Lee ,  Kyuseung Han ,  Tae Wook Kang ,  Sung Eun Kim ,  Hyuk Kim ,  Kyung Hwan Park ,  Hyung-Il Park ,  Kyung Jin Byun ,  Kwang Il Oh ,  In Gi Lim

IPC: H04N7/52 ,  H04N7/01 ,  H04N7/08 ,  H04N7/088 ,  H04N21/236 ,  H04N21/488 ,  H04N5/278

Abstract: Disclosed is a network-on-chip including a first data converter that receives first image data and second image data from at least one image sensor and encodes one image data among the first image data and the second image data, into first data, based on whether the first image data is identical to the second image data and a second data converter that receives non-image data from at least one non-image sensor and encodes the received non-image data into second data. The network-on-chip outputs the first data and the second data to transmit the first data and the second data to an external server at a burst length.

公开(公告)号：US12147263B2

公开(公告)日：2024-11-19

申请号：US17847636

申请日：2022-06-23

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kyuseung Han ,  Tae Wook Kang ,  Sung Eun Kim ,  Hyuk Kim ,  Hyung-Il Park ,  Kwang Il Oh ,  Jae-Jin Lee

IPC: G06F1/00 ,  G06F1/10 ,  G06F15/78

Abstract: A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.

公开(公告)号：US11775715B2

公开(公告)日：2023-10-03

申请号：US17116637

申请日：2020-12-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kyuseung Han ,  Sukho Lee ,  Jae-Jin Lee

IPC: G06F30/331 ,  G06F30/32 ,  G06F30/327 ,  G06F30/323 ,  G06F13/12

CPC classification number: G06F30/331 ,  G06F13/12 ,  G06F30/32 ,  G06F30/323 ,  G06F30/327 ,  G06F2213/0038 ,  G06F2213/3808

Abstract: Disclosed is a method of operating a system-on-chip automatic design device. The system-on-chip automatic design device includes a first synthesizer and a second synthesizer. The method includes generating a first code, based on information of a first signal and information of a second signal that are used in a first IP (Intellectual Property) block, classifying a first signal code corresponding to the first signal and a second signal code corresponding to the second signal from the first code, synthesizing, through the first synthesizer, a first communication architecture configured to transmit the first signal, based on the classified first signal code, and synthesizing, through the second synthesizer, a second communication architecture configured to transmit the second signal based on the classified second signal code.

公开(公告)号：US10340903B2

公开(公告)日：2019-07-02

申请号：US15725905

申请日：2017-10-05

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Woojoo Lee ,  Jae-Jin Lee ,  Sukho Lee ,  Kyuseung Han ,  Sang Pil Kim ,  Young Hwan Bae

IPC: H03K3/012 ,  H03K5/134 ,  H03K5/00

Abstract: Provided is a semiconductor device including a target circuit, a monitoring circuit, and a voltage controller. The target circuit includes a transistor. The monitoring circuit is configured to measure a temperature of the target circuit or measure a delay time between an input and an output of the target circuit. The voltage controller is configured to adjust a driving voltage for driving the target circuit or a back-bias voltage for adjusting a threshold voltage of the transistor by referring to at least one of the temperature and the delay time. As the temperature increases, the delay time decreases.

公开(公告)号：US12225464B2

公开(公告)日：2025-02-11

申请号：US17552766

申请日：2021-12-16

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Hyuk Kim ,  Hyung-Il Park ,  Tae Wook Kang ,  Sung Eun Kim ,  Mi Jeong Park ,  Kyung Jin Byun ,  Kwang Il Oh ,  Sukho Lee ,  Jae-Jin Lee ,  In Gi Lim ,  Kyuseung Han

IPC: H04W52/02 ,  H04B13/00

Abstract: Disclosed is an operating method of a user communication device, which includes receiving a wakeup signal from a stationary communication device over a first human body communication channel, the wakeup signal having a frequency in a low frequency band, switching from a standby mode to a wakeup mode in response to the wakeup signal, and receiving a data signal from the stationary communication device over the first human body communication channel during the wakeup mode, and the first human body communication channel is provided by a body of a user of the user communication device.

公开(公告)号：US11470018B2

公开(公告)日：2022-10-11

申请号：US16556905

申请日：2019-08-30

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kyuseung Han ,  Sukho Lee ,  Jae-Jin Lee ,  Sang Pil Kim ,  Young Hwan Bae ,  Kyung Jin Byun

IPC: H04L49/109 ,  H04L12/42 ,  G06F11/07

Abstract: Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.

公开(公告)号：US11086385B2

公开(公告)日：2021-08-10

申请号：US16165878

申请日：2018-10-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sukho Lee ,  Jae-Jin Lee ,  Kyuseung Han

IPC: G06F1/324 ,  G06F1/08 ,  G06T1/20 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/28 ,  G06F11/34

Abstract: Provided is a graphics processing unit and an operation method thereof. The graphics processing unit includes a plurality of cores in which a delay time between an input and an output decreases according to an increase of a temperature, a temperature monitoring and sorting circuit configured to monitor a temperature of each of the plurality of cores, and a controller configured to control a clock frequency and a power supply of the plurality of cores based on a drivable clock frequency of a core having the lowest temperature among temperatures of each of the plurality of monitored cores.