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1.发明授权Systems and methods of allocating device testing resources to sites of a probe card 有权将设备测试资源分配给探针卡的站点的系统和方法公开(公告)号：US07279919B2
公开(公告)日：2007-10-09
申请号：US11035580
申请日：2005-01-14
IPC分类号： G01R31/26
CPC分类号： G01R31/31926
摘要： Systems and methods of allocating device testing resources are described. In one aspect, a system for allocating m resources for testing devices to n sites of a probe card configured to electrically connect to respective test site locations on a substrate, where m and n are integers and m
摘要翻译： 描述了分配设备测试资源的系统和方法。 在一个方面，一种用于将测试设备的m个资源分配给探针卡的n个位置的系统，其被配置为电连接到衬底上的相应测试位置位置，其中m和n是整数，并且m
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2.发明授权Test system and method for testing electronic devices using a pipelined testing architecture 有权使用流水线测试架构测试电子设备的测试系统和方法公开(公告)号：US08347156B2
公开(公告)日：2013-01-01
申请号：US12821027
申请日：2010-06-22
CPC分类号： G01R31/31903 , G01R31/31926
摘要： A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.
摘要翻译： 用于对被测设备（DUT）进行测试的测试系统包括存储用于对DUT进行测试的测试数据的存储设备，用于生成测试数据的共享处理器，将测试数据存储在存储设备中并产生测试控制 信号，包括用于执行测试的一个或多个测试指令，并且对于每个DUT，被配置为从共享处理器接收测试控制信号的专用处理器，并且响应于测试控制信号，传送测试数据之一 测试指令到DUT以执行该测试指令并验证该测试指令的完成。
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3.发明授权Test system and method for testing electronic devices using a pipelined testing architecture 有权使用流水线测试架构测试电子设备的测试系统和方法公开(公告)号：US07743304B2
公开(公告)日：2010-06-22
申请号：US11357480
申请日：2006-02-17
CPC分类号： G01R31/31903 , G01R31/31926
摘要： A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.
摘要翻译： 用于对被测设备（DUT）进行测试的测试系统包括存储用于对DUT进行测试的测试数据的存储设备，用于生成测试数据的共享处理器，将测试数据存储在存储设备中并产生测试控制 信号，包括用于执行测试的一个或多个测试指令，并且对于每个DUT，被配置为从共享处理器接收测试控制信号的专用处理器，并且响应于测试控制信号，传送测试数据之一 测试指令到DUT以执行该测试指令并验证该测试指令的完成。
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4.发明申请TEST SYSTEM AND METHOD FOR TESTING ELECTRONIC DEVICES USING A PIPELINED TESTING ARCHITECTURE 有权使用管道测试架构测试电子设备的测试系统和方法公开(公告)号：US20110145645A1
公开(公告)日：2011-06-16
申请号：US12821027
申请日：2010-06-22
IPC分类号： G06F11/00
CPC分类号： G01R31/31903 , G01R31/31926
摘要： A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.
摘要翻译： 用于对被测设备（DUT）进行测试的测试系统包括存储用于对DUT进行测试的测试数据的存储设备，用于生成测试数据的共享处理器，将测试数据存储在存储设备中并产生测试控制 信号，包括用于执行测试的一个或多个测试指令，并且对于每个DUT，被配置为从共享处理器接收测试控制信号的专用处理器，并且响应于测试控制信号，传送测试数据之一 测试指令到DUT以执行该测试指令并验证该测试指令的完成。
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公开(公告)号：US20090055690A1
公开(公告)日：2009-02-26
申请号：US11895512
申请日：2007-08-24
申请人： Edmundo De La Puente
发明人： Edmundo De La Puente
IPC分类号： G06F11/00
CPC分类号： G06F11/273
摘要： In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for input in parallel to at least two devices under test; inputting in parallel to the testing device at least two response signals, each response signal produced by one of the at least two devices under test; storing the response signals received in parallel in a storage device; and serially outputting the response signals from the storage device.
摘要翻译： 根据本发明的一个实施例，提供了一种用于从被测试的多个设备获得测试数据的方法和装置。 这可以根据一个实施例通过从测试装置输出用于并行输入到至少两个被测器件的测试信号来实现; 与所述测试装置平行地输入至少两个响应信号，由所述至少两个被测设备之一产生的每个响应信号; 将并行接收的响应信号存储在存储设备中; 并从存储装置串行地输出响应信号。
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6.发明申请Inverted mesa quartz crystal time base reference for automatic test equipment 审中-公开倒置台面石英晶体时基参考用于自动测试设备公开(公告)号：US20080169730A1
公开(公告)日：2008-07-17
申请号：US11652352
申请日：2007-01-11
申请人： Romi Mayder , Edmundo De La Puente
发明人： Romi Mayder , Edmundo De La Puente
摘要： An inverted mesa quartz crystal oscillator suitable as a time base reference for automatic test equipment is presented. The inverted mesa quartz crystal may be formed by ion beam etching a mesa in a quartz crystal substrate.
摘要翻译： 介绍了适用于自动测试设备时基参考的倒置台面石英晶体振荡器。 倒置的台面石英晶体可以通过离子束蚀刻石英晶体衬底中的台面形成。
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7.发明授权Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors 有权存储器测试仪使用任意的动态映射将矢量序列化为传输的子向量，并将接收的子向量序列化为向量公开(公告)号：US07076714B2
公开(公告)日：2006-07-11
申请号：US10683796
申请日：2003-10-10
申请人： John H Cook, III , Alan S Krech, Jr. , Stephen D Jordan , Edmundo De La Puente , John M Freesman
发明人： John H Cook, III , Alan S Krech, Jr. , Stephen D Jordan , Edmundo De La Puente , John M Freesman
CPC分类号： G11C29/56004 , G11C16/04 , G11C29/56
摘要： The problem of sequentially “squeezing” small fields of data in a larger data path in and out of a memory device can be solved in an algorithmically driven memory tester by defining sub-vectors to represent data in the small field, where a sequence of sub-vectors represents the data that would be represented by a full sized vector if such a full sized vector could be applied to the DUT. A programming construct in the programming language of the algorithmically driven memory tester allows sub-vectors to be defined, as well as an arbitrary mapping that each is to have. The arbitrary mapping is not static, but changes dynamically as different sub-vectors are encountered. Arbitrary dynamic mappings change as sub-vectors are processed, and may include the notion that, during the activity for a sub-vector, this (or these) bit(s) of a vector do not (presently) map to any pin at all of the DUT. The arbitrary dynamic mapping is implemented by a collection of MUX's configured by data stored ahead of time in an SRAM, in accordance with what defining program constructs are encountered by the compiler as it processes the test program. A dynamic reverse mapper, also a collection of MUX's similarly controlled by an SRAM, serves as a de-serializer that assembles a sequence of received sub-vectors into a final received full-sized vector.
摘要翻译： 可以在算法驱动的存储器测试器中通过定义子向量来表示小字段中的数据来解决在存储器件中的较大数据路径中顺序地“挤压”小数据数据的问题，其中子序列 - 如果这样的全尺寸向量可以应用于DUT，则向量表示将由全尺寸向量表示的数据。 算法驱动的内存测试器的编程语言中的编程结构允许定义子向量，以及每个都具有的任意映射。 任意映射不是静态的，但是随着不同的子向量遇到动态变化。 任意动态映射随着子向量被处理而改变，并且可以包括在子向量的活动期间，向量的（或这些）比特（目前）不会（至少）映射到任何引脚的概念 的DUT。 根据编译器在处理测试程序时遇到的定义程序构造的任何动态映射由通过SRAM中提前存储的数据配置的MUX集合来实现。 动态反向映射器，也是由SRAM类似地控制的MUX的集合，用作解串器，其将接收的子向量的序列组装成最终接收的全尺寸向量。
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8.发明授权Algorithmically programmable memory tester with test sites operating in a slave mode 有权具有在从模式下运行的测试站点的算法可编程存储器测试器公开(公告)号：US06779140B2
公开(公告)日：2004-08-17
申请号：US09896474
申请日：2001-06-29
IPC分类号： G11C2900
CPC分类号： G11C29/56 , G01R31/31907
摘要： A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs. There also is a suspend/resume test program execution mechanism that assists one test program in temporarily interrupting the others to allow time for a change within one or more of the Test Sites of a measurement parameter, such as a voltage comparison threshold.
摘要翻译： 用于记忆测试仪的测试站由一个或多个测试站组成，每个测试站点各自具有算术可控性，每个测试站点可以处理多达六十四个通道，并且可以结合在一起以形成多站点测试站 两个或多个测试站点。 多达9个测试站点可以作为单个多站点测试站绑定在一起。 保税测试站点仍然以最高的速度运行，当他们没有绑定时能够实现。 为了实现这一点，有必要实施某些编程约定，并提供与在绑定的测试站点上单独测试程序同时启动有关的某些内务管理功能，以及与单独的测试程序之间的测试程序限定符结果的传播和同步有关。 还有一个暂停/恢复测试程序执行机制，协助一个测试程序临时中断其他测试程序，以便在测量参数的一个或多个测试站点内进行更改，例如电压比较阈值。
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公开(公告)号：US07827452B2
公开(公告)日：2010-11-02
申请号：US11895512
申请日：2007-08-24
申请人： Edmundo De La Puente
发明人： Edmundo De La Puente
IPC分类号： G01R31/28
CPC分类号： G06F11/273
摘要： In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for input in parallel to at least two devices under test; inputting in parallel to the testing device at least two response signals, each response signal produced by one of the at least two devices under test; storing the response signals received in parallel in a storage device; and serially outputting the response signals from the storage device.
摘要翻译： 根据本发明的一个实施例，提供了一种用于从被测试的多个设备获得测试数据的方法和装置。 这可以根据一个实施例通过从测试装置输出用于并行输入到至少两个被测器件的测试信号来实现; 与所述测试装置平行地输入至少两个响应信号，由所述至少两个被测设备之一产生的每个响应信号; 将并行接收的响应信号存储在存储设备中; 并从存储装置串行地输出响应信号。
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公开(公告)号：US20060158203A1
公开(公告)日：2006-07-20
申请号：US11035580
申请日：2005-01-14
IPC分类号： G01R31/02
CPC分类号： G01R31/31926
摘要： Systems and methods of allocating device testing resources are described. In one aspect, a system for allocating m resources for testing devices to n sites of a probe card configured to electrically connect to respective test site locations on a substrate, where m and n are integers and m
摘要翻译： 描述了分配设备测试资源的系统和方法。 在一个方面，一种用于将测试设备的m个资源分配给探针卡的n个位置的系统，其被配置为电连接到衬底上的相应测试位置位置，其中m和n是整数，并且m
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