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1.发明申请SYSTEM, METHODS AND APPARATUS USING VIRTUAL APPLIANCES IN A SEMICONDUCTOR TEST ENVIRONMENT 有权系统，方法和设备在半导体测试环境中使用虚拟设备公开(公告)号：US20140189430A1
公开(公告)日：2014-07-03
申请号：US13821559
申请日：2010-09-07
CPC分类号： G06F11/0712 , G01R31/2834 , G01R31/31907 , G05B19/41875 , G05B2219/45031 , G06F9/45533 , G06F11/2205 , G06F11/2273 , G06F11/261 , G06F11/301
摘要： In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance.
摘要翻译： 在一个实施例中，半导体测试控制系统包括具有多个硬件资源的计算机系统; 安装在计算机系统上的管理程序; 以及安装在计算机系统上的测试台控制器。 管理程序虚拟化硬件资源，并且向至少一个虚拟设备中的每一个提供对相应虚拟硬件资源组的访问。 硬件资源的每个虚拟集合使其相应的虚拟设备与半导体测试系统的至少第一方面进行控制通信，从而使得相应的虚拟设备能够测试相应类型的半导体器件。 测试台控制器正在控制与i）半导体测试系统的至少第二方面的通信，以及ii）至少一个虚拟设备中的每一个。
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2.发明授权System and method for testing circuitry using an externally generated signature 有权使用外部生成的签名测试电路的系统和方法公开(公告)号：US07131046B2
公开(公告)日：2006-10-31
申请号：US10308323
申请日：2002-12-03
IPC分类号： G16R31/28
CPC分类号： G01R31/318335 , G01R31/31705 , G01R31/318307
摘要： A system and method that enables testing of circuitry using an externally generated signature. An external tester is arranged external to a device under test (DUT). Such external tester is operable to input test data to the DUT, receive output data from the DUT, and generate a signature for at least a portion of such received output data. The external tester compares the generated signature with an expected signature to determine whether the DUT is functioning as expected. If the generated signature fails to match an expected signature, then error data can be written to an error map log. Preferably, further interaction with the DUT is not required after detecting that a generated signature fails to match an expected signature in order to perform such error evaluation. Thus, error evaluation can be performed concurrently with testing of the DUT. Mask data may be stored in a compressed form, and decompressed and used for masking certain non-deterministic output bits in generating the signature.
摘要翻译： 一种使用外部生成的签名测试电路的系统和方法。 外部测试仪设置在待测器件（DUT）的外部。 这种外部测试器可操作以将测试数据输入到DUT，从DUT接收输出数据，并且生成用于所接收的输出数据的至少一部分的签名。 外部测试仪将生成的签名与预期的签名进行比较，以确定DUT是否按预期运行。 如果生成的签名无法匹配预期签名，则可以将错误数据写入错误映射日志。 优选地，在检测到生成的签名不能匹配预期签名以执行这种错误评估之后，不需要与DUT的进一步的交互。 因此，可以与DUT的测试同时执行错误评估。 掩模数据可以以压缩形式存储，并且解压缩并用于在生成签名时屏蔽某些非确定性输出位。
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公开(公告)号：US20130138383A1
公开(公告)日：2013-05-30
申请号：US13700715
申请日：2011-05-27
IPC分类号： G06F17/00
CPC分类号： G01R31/31908 , G01R31/2834 , G06F11/263 , G06F11/2733 , G06F17/00 , G11C29/56
摘要： A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT.
摘要翻译： 用于自动化测试设备的系统。 在一个实施例中，该系统包括被编程为提供测试模式的可配置集成电路（IC）和到至少一个被测器件（DUT）的接口。 该系统还包括到至少一个DUT的连接，其中连接被直接耦合在可配置IC和至少一个DUT之间。
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4.发明授权Test system and method for testing electronic devices using a pipelined testing architecture 有权使用流水线测试架构测试电子设备的测试系统和方法公开(公告)号：US08347156B2
公开(公告)日：2013-01-01
申请号：US12821027
申请日：2010-06-22
CPC分类号： G01R31/31903 , G01R31/31926
摘要： A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.
摘要翻译： 用于对被测设备（DUT）进行测试的测试系统包括存储用于对DUT进行测试的测试数据的存储设备，用于生成测试数据的共享处理器，将测试数据存储在存储设备中并产生测试控制 信号，包括用于执行测试的一个或多个测试指令，并且对于每个DUT，被配置为从共享处理器接收测试控制信号的专用处理器，并且响应于测试控制信号，传送测试数据之一 测试指令到DUT以执行该测试指令并验证该测试指令的完成。
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5.发明授权公开(公告)号：US08320235B2
公开(公告)日：2012-11-27
申请号：US11357227
申请日：2006-02-17
申请人： Erik H. Volkerink , Alan Hart
发明人： Erik H. Volkerink , Alan Hart
IPC分类号： H04L12/26
CPC分类号： G06F11/2007 , G06F11/2025
摘要： A self-repair system provides resource failure tolerance using an interconnection network that provides interconnection information identifying connections between system resources, redundant resources and ports that are connectable to consumers of the system resources. A controller identifies both defective system resources and the affected sinks connected to the defective system resources from the interconnection network. The controller further identifies compatible resources from the system resources and redundant resources that are capable of replacing the defective system resources for each of the affected sinks from the interconnection network. The controller determines a respective cost associated with each of the compatible resources, and in response to the determined costs, selects at least one of the compatible resources as a replacement resource for each of the defective system resources. The controller further configures the interconnection network to connect the replacement resources to the affected ports instead of the defective system resources.
摘要翻译： 自修复系统使用互连网络提供资源容错，其提供识别可连接到系统资源的消费者的系统资源，冗余资源和端口之间的连接的互连信息。 控制器从互连网络识别连接到有缺陷的系统资源的有缺陷的系统资源和受影响的汇点。 控制器还从系统资源和冗余资源中识别出能够从互连网络替换每个受影响的接收器的有缺陷的系统资源的兼容资源。 控制器确定与每个兼容资源相关联的相应成本，并且响应于确定的成本，选择至少一个兼容资源作为每个缺陷系统资源的替换资源。 控制器还配置互连网络以将替换资源连接到受影响的端口，而不是有缺陷的系统资源。
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6.发明授权Test system and method for testing electronic devices using a pipelined testing architecture 有权使用流水线测试架构测试电子设备的测试系统和方法公开(公告)号：US07743304B2
公开(公告)日：2010-06-22
申请号：US11357480
申请日：2006-02-17
CPC分类号： G01R31/31903 , G01R31/31926
摘要： A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.
摘要翻译： 用于对被测设备（DUT）进行测试的测试系统包括存储用于对DUT进行测试的测试数据的存储设备，用于生成测试数据的共享处理器，将测试数据存储在存储设备中并产生测试控制 信号，包括用于执行测试的一个或多个测试指令，并且对于每个DUT，被配置为从共享处理器接收测试控制信号的专用处理器，并且响应于测试控制信号，传送测试数据之一 测试指令到DUT以执行该测试指令并验证该测试指令的完成。
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公开(公告)号：US09429623B2
公开(公告)日：2016-08-30
申请号：US13700715
申请日：2011-05-27
IPC分类号： G06F11/263 , G06F17/00 , G11C29/56 , G01R31/28 , G01R31/319 , G06F11/273
CPC分类号： G01R31/31908 , G01R31/2834 , G06F11/263 , G06F11/2733 , G06F17/00 , G11C29/56
摘要： A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT.
摘要翻译： 用于自动化测试设备的系统。 在一个实施例中，该系统包括被编程为提供测试模式的可配置集成电路（IC）和到至少一个被测器件（DUT）的接口。 该系统还包括到至少一个DUT的连接，其中连接被直接耦合在可配置IC和至少一个DUT之间。
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公开(公告)号：US07412639B2
公开(公告)日：2008-08-12
申请号：US10155651
申请日：2002-05-24
申请人： Erik H. Volkerink , Ajay Koche
发明人： Erik H. Volkerink , Ajay Koche
IPC分类号： G01R31/28
CPC分类号： G01R31/318505 , G01R31/2884 , G01R31/318511 , G01R31/318533
摘要： A system and method in which a plurality of dice on a semiconductor wafer are interconnected to enable efficient testing thereof. In certain embodiments a plurality of dice are interconnected in a manner that enables test data to be communicated from a tester system to a plurality of dice for concurrent testing of such plurality of dice. Depending on the amount of interconnection, all or a portion of each of the plurality of dice may be tested concurrently. In certain embodiments, a plurality of dice are interconnected in a manner that enables test data to be communicated from one die to at least one other die. In certain embodiments, a plurality of dice are interconnected in a manner that enables such dice to be tested concurrently while maintaining a repeatable pattern at the reticle level for fabricating such dice.
摘要翻译： 将半导体晶片上的多个骰子互连以实现其有效测试的系统和方法。 在某些实施例中，多个骰子以使得能够将测试数据从测试器系统传送到多个骰子用于并行测试这样的多个骰子的方式相互连接。 根据互连量，可以同时测试多个骰子中的每一个的全部或一部分。 在某些实施例中，以能够使测试数据从一个管芯传递到至少一个其它管芯的方式互连多个管芯。 在某些实施例中，以能够同时测试这样的骰子的方式互连多个骰子，同时在掩模版级别保持可重复的图案以制造这种骰子。
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公开(公告)号：US07386777B2
公开(公告)日：2008-06-10
申请号：US10818101
申请日：2004-04-05
IPC分类号： G01R31/28
CPC分类号： G01R31/31921 , G01R31/31917
摘要： Representative embodiments are generally directed to storing compressed test pattern data on an automated test equipment (ATE) device. In one embodiment, the test pattern data is compressed according to a linear feedback shift register (LFSR). The LFSR may possess a low probability of occurrence of linear dependencies associated with compression of stimulus patterns to enable relatively highly compacted patterns to be compressed. Additionally or alternatively, repeat-filled test pattern data is run length encoded using variable length code words to facilitate parallel decompression within the ATE device.
摘要翻译： 代表性实施例通常涉及将压缩测试图案数据存储在自动测试设备（ATE）设备上。 在一个实施例中，测试图案数据根据线性反馈移位寄存器（LFSR）被压缩。 LFSR可以具有与刺激图案的压缩相关联的线性依赖性的低发生概率，以使得能够压缩相对高度压缩的图案。 另外或替代地，重复填充的测试模式数据使用可变长度码字进行游程长度编码，以便于ATE设备内的并行解压缩。
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10.发明申请TEST SYSTEM AND METHOD FOR TESTING ELECTRONIC DEVICES USING A PIPELINED TESTING ARCHITECTURE 有权使用管道测试架构测试电子设备的测试系统和方法公开(公告)号：US20110145645A1
公开(公告)日：2011-06-16
申请号：US12821027
申请日：2010-06-22
IPC分类号： G06F11/00
CPC分类号： G01R31/31903 , G01R31/31926
摘要： A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.
摘要翻译： 用于对被测设备（DUT）进行测试的测试系统包括存储用于对DUT进行测试的测试数据的存储设备，用于生成测试数据的共享处理器，将测试数据存储在存储设备中并产生测试控制 信号，包括用于执行测试的一个或多个测试指令，并且对于每个DUT，被配置为从共享处理器接收测试控制信号的专用处理器，并且响应于测试控制信号，传送测试数据之一 测试指令到DUT以执行该测试指令并验证该测试指令的完成。
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