Special contact points for accessing internal circuitry of an integrated circuit
    4.
    发明申请
    Special contact points for accessing internal circuitry of an integrated circuit 失效
    用于访问集成电路内部电路的特殊接点

    公开(公告)号:US20010020747A1

    公开(公告)日:2001-09-13

    申请号:US09753309

    申请日:2000-12-29

    Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.

    Abstract translation: 本发明的一个实施例涉及包括接合焊盘和特殊接触焊盘或点的集成电路。 接合焊盘用于将集成电路作为整体与外部电路接口,并且将被连接到封装或电路板。 接合焊盘以预定的对准方式设置在管芯上,例如外围,栅格或中心对准。 特殊接触焊盘用于向内部电路提供外部测试模式和/或外部监测测试内部电路的结果。 特别的接触垫可以有利地以高度的位置自由度位于集成电路上。 对于一个实施例,特殊接触焊盘可以在与焊盘不同于对准的位置处设置在管芯上。 特殊的接触焊盘可以小于接合焊盘,以便不会由于特殊的接触垫而增加管芯的尺寸。 特殊接触点也可以用于在芯片或封装级别外部编程内部电路(例如非易失性电路)。 特殊接触点也可用于选择故障电路的冗余电路。

    Method for testing signal paths between an integrated circuit wafer and a wafer tester
    5.
    发明申请
    Method for testing signal paths between an integrated circuit wafer and a wafer tester 失效
    用于测试集成电路晶片和晶圆测试仪之间的信号路径的方法

    公开(公告)号:US20040148122A1

    公开(公告)日:2004-07-29

    申请号:US10756477

    申请日:2004-01-12

    CPC classification number: G01R31/3167

    Abstract: Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.

Patent Agency Ranking