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    Differential poly doping and circuits therefrom
    6.
    发明授权
    Differential poly doping and circuits therefrom 有权
    差分多掺杂及其电路

    公开(公告)号：US08114729B2

    公开(公告)日：2012-02-14

    申请号：US11870255

    申请日：2007-10-10

    申请人： Shashank Ekbote ,  Kamel Benaissa ,  Greg C. Baldwin ,  Borna Obradovic

    发明人： Shashank Ekbote ,  Kamel Benaissa ,  Greg C. Baldwin ,  Borna Obradovic

    IPC分类号： H01L21/8238

    CPC分类号： G11C11/412 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/32155 ,  H01L21/823842 ,  H01L27/0922 ,  Y10S257/903

    摘要： A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant.

    摘要翻译： 一种制造CMOS集成电路的方法及其集成电路包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，以及在栅极电介质上形成多晶硅。 多晶硅层的一部分被掩蔽，并且执行第一掺杂剂类型的预栅极蚀刻注入到多晶硅层的未屏蔽部分中，其中多晶硅层的掩模部分被保护免受第一掺杂剂的影响。 多晶硅层被图案化以形成多个多晶硅栅极和多条多晶硅线，其中掩模部分包括将PMOS器件的多晶硅栅极耦合到NMOS器件的多晶硅栅极的至少一条多晶硅线路。 然后完成集成电路的制造，其中集成电路包括形成在掩模部分中的至少一个第一区域，该第一区域在预栅极蚀刻植入物的多晶硅栅极中缺少第一掺杂剂，以及形成在未掩模部分中的至少一个第二区域 在栅极蚀刻植入物的多晶硅栅极中具有第一掺杂剂。

    DIFFERENTIAL OFFSET SPACER
    7.
    发明申请
    DIFFERENTIAL OFFSET SPACER 有权
    差异偏移距离

    公开(公告)号：US20090098695A1

    公开(公告)日：2009-04-16

    申请号：US11870241

    申请日：2007-10-10

    申请人： Shashank Ekbote ,  Deborah J. Riley ,  Borna Obradovic

    发明人： Shashank Ekbote ,  Deborah J. Riley ,  Borna Obradovic

    IPC分类号： H01L21/8238 ,  H01L21/8244

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823864 ,  H01L27/11

    摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed.

    摘要翻译： 制造CMOS集成电路的方法包括以下步骤：使用该表面在NMOS和PMOS区域中提供具有半导体表面的衬底，在其上形成栅极电介质和多个栅电极。 形成包括顶层和组成不同底层的多层偏移间隔堆叠，并且蚀刻多层间隔堆叠以在栅电极的侧壁上形成偏置间隔物。 设计成利用较薄的偏移间隔物的晶体管被​​第一掩模材料覆盖，并且被设计成利用更厚的偏移间隔物的晶体管被​​图案化并且首先被注入。 去除顶层的至少一部分以在栅电极的侧壁上留下较薄的偏移间隔物。 设计成利用较厚的偏移间隔物的晶体管被​​第二掩模材料覆盖，并且设计成利用较薄的偏移间隔物的晶体管被​​图案化并且被第二次注入。 然后完成集成电路的制造。

    MOS DEVICE AND PROCESS HAVING LOW RESISTANCE SILICIDE INTERFACE USING ADDITIONAL SOURCE/DRAIN IMPLANT
    8.
    发明申请
    MOS DEVICE AND PROCESS HAVING LOW RESISTANCE SILICIDE INTERFACE USING ADDITIONAL SOURCE/DRAIN IMPLANT 有权
    具有附加源/漏极植入物的低电阻硅化物界面的MOS器件和工艺

    公开(公告)号：US20090057759A1

    公开(公告)日：2009-03-05

    申请号：US11848962

    申请日：2007-08-31

    申请人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

    发明人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

    IPC分类号： H01L21/8238 ,  H01L29/94

    CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

    摘要： An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.

    摘要翻译： 集成电路（IC）包括半导体衬底，形成在衬底中或衬底上的至少一个MOS晶体管，所述MOS晶体管包括掺杂有第一掺杂剂类型的源极和漏极，所述第一掺杂类型具有介于其间的第二掺杂剂类型的沟道区，以及 栅电极和沟道区上的栅极绝缘体。 形成低电阻接触的硅化物层位于源极和漏极的表面部分的界面区域。 在界面区域，第一掺杂剂的化学浓度为至少5×10 20 cm -3。 根据本发明的硅化物界面提供具有低硅化物界面电阻，低管密度的MOS晶体管，对短沟道行为具有可接受的小的影响。

    CD gate bias reduction and differential N+ poly doping for CMOS circuits
    9.
    发明授权
    CD gate bias reduction and differential N+ poly doping for CMOS circuits 有权
    用于CMOS电路的CD栅偏压减小和差分N +多掺杂

    公开(公告)号：US07718482B2

    公开(公告)日：2010-05-18

    申请号：US11928872

    申请日：2007-10-30

    申请人： Shashank Ekbote ,  Borna Obradovic ,  Greg C. Baldwin

    发明人： Shashank Ekbote ,  Borna Obradovic ,  Greg C. Baldwin

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823842 ,  H01L27/11

    摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.

    摘要翻译： 一种制造CMOS集成电路的方法包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，在栅极介质层上形成多晶硅层。 图案化多晶硅层，同时未掺杂以形成包含栅极的多个多晶硅。 第一模式用于保护多个PMOS器件，并且执行第一n型注入以掺杂多个NMOS器件的栅极和源极/漏极区域。 第二模式用于保护PMOS器件以及用于多个NMOS器件的一部分的源极/漏极和栅极，并且执行第二n型注入以掺杂其它NMOS器件的栅极。