公开(公告)号：US20220360259A1

公开(公告)日：2022-11-10

申请号：US17308423

申请日：2021-05-05

Applicant: GaN Systems Inc.

Inventor： Ruoyu HOU ,  Juncheng LU ,  Larry SPAZIANI

IPC: H03K17/0812 ,  H03K17/16

Abstract: An active gate voltage control circuit for a gate driver of a power semiconductor switching device comprising a power semiconductor transistor, such as a GaN HEMT, provides active gate voltage control comprising current burst mode operation and protection mode operation. The gate-source turn-on voltage Vgs(on) is increased in burst mode operation, to allow for a temporary increase of saturation current. In protection mode operation, a multi-stage turn-off may be implemented, comprising reducing Vgs(on) to implement fast soft turn-off, followed by full turn-off to bring Vgs(on) below threshold voltage, to reduce switching transients such as Vds spikes. Circuits of example embodiments provide for burst mode operation for enhanced saturation current, to increase robustness of enhancement mode GaN power switching devices, e.g. under overcurrent and short circuit conditions, or to provide active gate voltage control which adjusts dynamically to specific operating conditions or events.

公开(公告)号：US20240372478A1

公开(公告)日：2024-11-07

申请号：US18310416

申请日：2023-05-01

Applicant: GAN SYSTEMS INC.

Inventor： Mahdi JEDARI ZARE ZADEH ,  Juncheng LU

IPC: H02M3/335 ,  H02M1/00 ,  H02M7/483

Abstract: A voltage converter circuit including a primary side circuit including four transistors connected in series between two voltage application nodes, and two capacitors coupled in series between the two voltage application nodes. A flying capacitor is connected between first circuit node and a second circuit node, where the first circuit node is between the first and second transistors in the transistor series, and the second circuit node is between the third and fourth transistors in the transistor series. A primary side transformer is connected between a third circuit node and a fourth circuit node, where the third circuit node is between the second and third transistors in the transistor series, and the fourth circuit node is between the first and second capacitors in the capacitor series.

公开(公告)号：US20230282540A1

公开(公告)日：2023-09-07

申请号：US17979970

申请日：2022-11-03

Applicant: GaN Systems Inc.

Inventor： Ruoyu HOU ,  Juncheng LU ,  Andrew DICKSON

IPC: H01L23/367 ,  H01L23/373 ,  H01L25/07 ,  H01L29/20

CPC classification number: H01L23/3672 ,  H01L23/3735 ,  H01L23/3731 ,  H01L25/072 ,  H01L29/2003

Abstract: A multi-zone substrate for a power stage assembly comprising at least one bottom-cooled semiconductor power switching device and driver components, for integration on a common substrate. A first zone provides electrical connections and a thermal pad for mounting at least one bottom-cooled semiconductor switching device, the first zone comprising dielectric and conductive layers which provide a power substrate optimized for thermal performance. A second zone provides electrical connections for mounting driver components, the second zone comprising dielectric and conductive layers providing a driver substrate optimized for electrical performance. For example, the first zone comprises a single layer metal interconnect structure with a first thermal resistance, the second zone comprises a multi-layer metal interconnect structure with a second thermal resistance, the first thermal resistance being less than the second thermal resistance. The power stage assembly may comprise a multi-zone substrate configured for a single switch, half-bridge or full-bridge switch topology.

公开(公告)号：US20240306348A1

公开(公告)日：2024-09-12

申请号：US18120046

申请日：2023-03-10

Applicant: GaN Systems Inc.

Inventor： Ruoyu HOU ,  Juncheng LU

IPC: H05K7/20 ,  H01L23/367 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K7/20409 ,  H01L23/3672 ,  H05K1/0216 ,  H05K1/185 ,  H05K2201/066 ,  H05K2201/10166

Abstract: A power stage assembly for improved thermal dissipation and EMC for top-cooled semiconductor power switching devices, e.g. high voltage, high current lateral GaN power transistors in embedded die packages. The power switching devices are mounted on a PCB substrate, with electrical connections between a bottom side of each device package and the PCB. Each device package has a thermal pad on the top-side. A heat-spreader is secured in thermal contact with the thermal pads of each device, and a heatsink is in thermal contact with the heat-spreader. The heat-spreader is a multilayer structure comprising: a thermally conductive metal substrate layer in contact with the heatsink; a conductive layer providing an EMC layer which is connected to power ground; a conductive layer defining large area thermal pads in thermal contact with thermal pads of each die; and dielectric material electrically isolating conductive layers of the heat-spreader.

公开(公告)号：US20190238062A1

公开(公告)日：2019-08-01

申请号：US16251696

申请日：2019-01-18

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Di CHEN ,  Larry SPAZIANI

IPC: H02M7/487 ,  H02M7/537 ,  H03K17/0412 ,  H03K17/12 ,  H03K17/284 ,  H03K17/60 ,  H03K17/687 ,  H01L29/739

Abstract: A 3-level T-type neutral point clamped (NPC) inverter/rectifier is disclosed in which neutral point clamping is dynamically enabled/disabled responsive to load, e.g. enabled at low load for operation in a first mode as a 3-level inverter/rectifier and disabled at high/peak load for operation in a second mode as a 2-level inverter/rectifier. When the neutral clamping leg is enabled only under low load and low current, middle switches S2 and S3 can be smaller, lower cost devices with a lower current rating. Si, SiC, GaN and hybrid implementations provide options to optimize efficiency for specific load ratios and applications. For reduced switching losses and enhanced performance of inverters based on Si-IGBT power switches, a hybrid implementation of the dual-mode T-type NPC inverter is proposed, wherein switches S1 and S4 comprise Si-IGBTs and switches S2 and S3 of the neutral clamping leg comprise GaN HEMTs. Applications include electric vehicle traction inverters.

公开(公告)号：US20220190825A1

公开(公告)日：2022-06-16

申请号：US17123316

申请日：2020-12-16

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Larry SPAZIANI

IPC: H03K17/687 ,  H03K17/567

Abstract: Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.

公开(公告)号：US20230402342A1

公开(公告)日：2023-12-14

申请号：US18094477

申请日：2023-01-09

Applicant: GaN Systems Inc.

Inventor： Di CHEN ,  Juncheng LU ,  Ahmad MIZAN ,  Ruoyu HOU ,  Abhinandan DIXIT

IPC: H01L23/367 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L23/3672 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor switching devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers, and wherein a first thermal pad on one side of the package and a second thermal pad on an opposite side of the package provides for dual-side cooling. Example embodiments of the dual-side cooled package may be based on a bottom-side cooled layup with a primary bottom-side thermal pad and a secondary top-side thermal pad, or a top-side cooled layup with primary top-side thermal pad and a secondary bottom side thermal pad, using layups with or without a leadframe. For example, the power semiconductor switching device comprises a GaN power transistor, such as a GaN HEMT rated for operation at ≥100V or ≥600V, for switching tens or hundreds of Amps.

公开(公告)号：US20210398875A1

公开(公告)日：2021-12-23

申请号：US17465345

申请日：2021-09-02

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Di CHEN ,  Larry SPAZIANI ,  Peter Anthony DI MASO

IPC: H01L23/367 ,  H01L23/538 ,  H01L29/778 ,  H01L29/20 ,  H01L25/11 ,  H01L23/498

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.

公开(公告)号：US20200185302A1

公开(公告)日：2020-06-11

申请号：US16705696

申请日：2019-12-06

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Di CHEN ,  Larry SPAZIANI ,  Peter Anthony DI MASO

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/498 ,  H01L29/20 ,  H01L25/11 ,  H01L29/778

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.