公开(公告)号：US20190214348A1

公开(公告)日：2019-07-11

申请号：US15867118

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

公开(公告)号：US10700013B2

公开(公告)日：2020-06-30

申请号：US15867118

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

公开(公告)号：US09927698B2

公开(公告)日：2018-03-27

申请号：US15234078

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jed H. Rankin ,  Adam C. Smith

IPC: G03F1/70 ,  G03F1/78 ,  G03F1/20 ,  G03F7/20 ,  H01L21/027 ,  B82Y10/00 ,  G06F17/50 ,  B82Y40/00 ,  H01J37/317

CPC classification number: G03F1/70 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/20 ,  G03F1/76 ,  G03F1/78 ,  G03F7/20 ,  G03F7/2022 ,  G03F7/2037 ,  G03F7/2063 ,  G03F7/7025 ,  G06F17/50 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01J37/3174 ,  H01L21/0274 ,  Y10S430/143

Abstract: A method and system for: forming a first rectangular shape with photomask writing equipment, using a first sub-threshold dosage on a photoresist layer of a photomask substrate; forming an overlapping second rectangular shape with the photomask writing equipment using a second sub-threshold dosage on the photoresist layer, the second rectangular shape being rotated relative to the first rectangular shape to form one of: a hexagonal overlap area and an octagonal overlap area, that exposes the photoresist layer to at least a threshold dosage; and forming a photomask, based on developing the exposed photoresist layer, to provide optical transmission corresponding to the one of: the hexagonal overlap area of at least the threshold dosage and the octagonal overlap area of at least the threshold dosage, for use by a photolithography system to write any of a contact, a via, or a curvilinear shape on an integrated circuit substrate.