公开(公告)号：US09754071B1

公开(公告)日：2017-09-05

申请号：US15048066

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haraprasad Nanjundappa ,  Basanth Jagannathan ,  Laura S. Chadwick ,  Dureseti Chidambarrao ,  Christopher V. Baiocco

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

公开(公告)号：US20170242952A1

公开(公告)日：2017-08-24

申请号：US15048066

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haraprasad Nanjundappa ,  Basanth Jagannathan ,  Laura S. Chadwick ,  Dureseti Chidambarrao ,  Christopher V. Baiocco

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

公开(公告)号：US09311443B2

公开(公告)日：2016-04-12

申请号：US14306715

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dureseti Chidambarrao ,  James A. Culp ,  Paul C. Parries ,  Ian P. Stobert

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  G03F7/70433 ,  G03F7/70633

Abstract: Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data.

Abstract translation: 用于在半导体光刻掩模设计工艺流程期间减少重叠误差的装置，方法和计算机程序产品。 该方法获得表示光掩模布局设计的密度特性的数据; 基于所获得的密度特征数据预测应力诱导位移; 并通过指定各个照片掩模设计形状的移位移动来预测补偿预测的位移来校正掩模布局设计数据。 为了获得表示密度特性的数据，该方法合并组合的数据以制作光掩模以获得完整的掩模版场数据集。 合并包括表示密度特征驱动应力效应的数据的合并。 然后计算合并的掩模版数据的密度特性数据。 为了预测应力引起的位移，该方法将所述密度特征数据输入到预测作为密度的函数的位移的编程模型中，并输出预测的移位数据。

公开(公告)号：US09305999B2

公开(公告)日：2016-04-05

申请号：US13778419

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/06 ,  H01L29/10 ,  H01L29/84 ,  H01L21/762

CPC classification number: H01L29/0603 ,  H01L21/76224 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/84

Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Abstract translation: 在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。 通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。 应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。 氧化硅材料沉积在深沟槽中，平坦化和凹陷。 去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。 应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。