公开(公告)号：US20180374753A1

公开(公告)日：2018-12-27

申请号：US15629884

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： BARTLOMIEJ J. PAWLAK ,  GUILLAUME BOUCHE ,  AJEY P. JACOB

IPC: H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06

Abstract: Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively.

公开(公告)号：US20160079242A1

公开(公告)日：2016-03-17

申请号：US14949481

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： GUILLAUME BOUCHE ,  Andy Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

公开(公告)号：US20180240883A1

公开(公告)日：2018-08-23

申请号：US15955989

申请日：2018-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： DANIEL CHANEMOUGAME ,  ANDRE LABONTE ,  RUILONG XIE ,  LARS LIEBMANN ,  NIGEL CAVE ,  GUILLAUME BOUCHE

IPC: H01L29/49 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/0217 ,  H01L21/28141 ,  H01L21/30604 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66689 ,  H01L29/66719 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L2924/13067

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

公开(公告)号：US20180204927A1

公开(公告)日：2018-07-19

申请号：US15408540

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： DANIEL CHANEMOUGAME ,  ANDRE LABONTE ,  RUILONG XIE ,  LARS LIEBMANN ,  NIGEL CAVE ,  GUILLAUME BOUCHE

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/4991 ,  H01L21/0217 ,  H01L21/28141 ,  H01L21/30604 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66689 ,  H01L29/66719 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L2924/13067

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.