公开(公告)号：US20160336515A1

公开(公告)日：2016-11-17

申请号：US15190365

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lawrence A. Clevenger ,  Chandrasekhar Narayan ,  Gregory A. Northrop ,  Carl J. Radens ,  Brian C. Sapp

IPC: H01L51/00 ,  H01L51/05 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L51/0012 ,  H01L51/0541 ,  Y10S977/742 ,  Y10S977/842

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

公开(公告)号：US10796056B2

公开(公告)日：2020-10-06

申请号：US16014287

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gregory A. Northrop ,  Lionel Riviere-Cazaux ,  Lars Liebmann ,  Kai Sun ,  Norihito Nakamoto

IPC: G06F30/00 ,  G06F30/392 ,  G03F1/36 ,  G06F30/398 ,  H01L21/78 ,  G06F111/04 ,  G06F111/20

Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.

公开(公告)号：US10522403B2

公开(公告)日：2019-12-31

申请号：US15868479

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. Stephens ,  Daniel Chanemougame ,  Ruilong Xie ,  Lars W. Liebmann ,  Gregory A. Northrop

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US20190392106A1

公开(公告)日：2019-12-26

申请号：US16014287

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gregory A. Northrop ,  Lionel Riviere-Cazaux ,  Lars Liebmann ,  Kai Sun ,  Norihito Nakamoto

IPC: G06F17/50 ,  G03F1/36

Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.

公开(公告)号：US09640765B2

公开(公告)日：2017-05-02

申请号：US15190365

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lawrence A. Clevenger ,  Chandrasekhar Narayan ,  Gregory A. Northrop ,  Carl J. Radens ,  Brian C. Sapp

IPC: H01L51/00 ,  H01L29/775 ,  H01L29/66 ,  B82Y40/00 ,  B82Y10/00 ,  H01L29/06 ,  H01L51/05

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L51/0012 ,  H01L51/0541 ,  Y10S977/742 ,  Y10S977/842

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

公开(公告)号：US20130328205A1

公开(公告)日：2013-12-12

申请号：US13490840

申请日：2012-06-07

Applicant: Globalfoundries Inc. ,  International Business Machines Corporation ,  STMircoelectronics Inc.

Inventor： Frank Johnson ,  Olivier Menut ,  Marc Tarabbia ,  Gregory A. Northrop

IPC: H01L23/52 ,  H01L21/768

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L27/11807 ,  H01L2027/11859 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括具有第一边界，与第一边界相反的第二边界，互连第一和第二边界的第三边界以及与第三边界相对的第四边界并互连第一和第二边界的标准单元。 标准单元还包括从第一边界延伸到第二边界的并行有效区域。 此外，标准单元具有从第三边界延伸到第四边界并且在有源区上延伸的平行栅极条。 切割掩模覆盖门条。 互连件定位在切割掩模上方并与选定的栅条形成电连接。