公开(公告)号：US10283584B2

公开(公告)日：2019-05-07

申请号：US15277583

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  Andrei Sidelnicov ,  El Mehdi Bazizi

IPC: H01L29/78 ,  H01L49/02 ,  H01L23/535 ,  H01L29/94

Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.

公开(公告)号：US10930777B2

公开(公告)日：2021-02-23

申请号：US15819825

申请日：2017-11-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ignasi Cortes Mayol ,  Alban Zaka ,  Tom Herrmann ,  El Mehdi Bazizi

IPC: H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.

公开(公告)号：US20180254343A1

公开(公告)日：2018-09-06

申请号：US15971419

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Alban Zaka ,  Ignasi Cortes Mayol

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L29/45 ,  H01L29/167 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7824 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A method of forming a semiconductor device includes forming a first well and a second well in a substrate, wherein the first well is doped with dopants of a first conductivity type and the second well is doped with dopants of a second conductivity type. A third well is formed within the first well, and a gate structure is formed above the substrate, the gate structure partially overlying at least the first and second wells. A first epi region is formed on the third well, wherein the first epi region is doped with second dopants of the second conductivity type, and a drain region is formed that is electrically coupled to the second well.

公开(公告)号：US20190157451A1

公开(公告)日：2019-05-23

申请号：US15819825

申请日：2017-11-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ignasi Cortes Mayol ,  Alban Zaka ,  Tom Herrmann ,  El Mehdi Bazizi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.

公开(公告)号：US20180090558A1

公开(公告)日：2018-03-29

申请号：US15277583

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  Andrei Sidelnicov ,  El Mehdi Bazizi

IPC: H01L49/02 ,  H01L23/535 ,  H01L29/36

CPC classification number: H01L28/60 ,  H01L23/535 ,  H01L29/94

Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.

公开(公告)号：US10283642B1

公开(公告)日：2019-05-07

申请号：US15957072

申请日：2018-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  El Mehdi Bazizi ,  Luca Pirro

IPC: H01L29/786 ,  H01L29/08

Abstract: Manufacturing techniques and related semiconductor devices are disclosed in which the channel region of analog transistors and/or transistors operated at higher supply voltages may be formed on the basis of a very thin semiconductor layer in an SOI configuration by incorporating a counter-doped region into the channel region at the source side of the transistor. The counter-doped region may be inserted prior to forming the gate electrode structure. With this asymmetric dopant profile in the channel region, superior transistor performance may be obtained, thereby obtaining a performance gain for transistors formed on the basis of a thin semiconductor base material required for the formation of sophisticated fully depleted transistor elements.

公开(公告)号：US10170614B2

公开(公告)日：2019-01-01

申请号：US15971419

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Alban Zaka ,  Ignasi Cortes Mayol

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L29/45 ,  H01L29/06 ,  H01L29/167 ,  H01L29/08 ,  H01L29/10

Abstract: A method of forming a semiconductor device includes forming a first well and a second well in a substrate, wherein the first well is doped with dopants of a first conductivity type and the second well is doped with dopants of a second conductivity type. A third well is formed within the first well, and a gate structure is formed above the substrate, the gate structure partially overlying at least the first and second wells. A first epi region is formed on the third well, wherein the first epi region is doped with second dopants of the second conductivity type, and a drain region is formed that is electrically coupled to the second well.

公开(公告)号：US20170317209A1

公开(公告)日：2017-11-02

申请号：US15198038

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Alban Zaka ,  Ignasi Cortes Mayol

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/167 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7824 ,  H01L21/26513 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: The present disclosure provides a semiconductor device including a substrate, a first well and a second well formed in the substrate, the first well being doped with dopants of a first conductivity type and the second well being doped with dopants of a second conductivity type, a third well within the first well, a gate structure partially formed over the first and second wells, and a first epi region on the third well and a drain region electrically coupled to the second well, the first epi region being doped with dopants of the second conductivity type.

公开(公告)号：US10121846B1

公开(公告)日：2018-11-06

申请号：US15620923

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  El Mehdi Bazizi ,  John Morgan

IPC: H01L49/02 ,  H01L27/06

Abstract: The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits.

公开(公告)号：US10038091B2

公开(公告)日：2018-07-31

申请号：US15198038

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Alban Zaka ,  Ignasi Cortes Mayol

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/167 ,  H01L29/06 ,  H01L29/45 ,  H01L21/265 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: The present disclosure provides a semiconductor device including a substrate, a first well and a second well formed in the substrate, the first well being doped with dopants of a first conductivity type and the second well being doped with dopants of a second conductivity type, a third well within the first well, a gate structure partially formed over the first and second wells, and a first epi region on the third well and a drain region electrically coupled to the second well, the first epi region being doped with dopants of the second conductivity type.