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    Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark
    1.
    发明授权
    Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark 有权
    在使用FinFET器件的集成电路产品上形成对准标记和覆盖标记的方法以及所得到的对准/覆盖标记

    公开(公告)号：US09275890B2

    公开(公告)日：2016-03-01

    申请号：US13834608

    申请日：2013-03-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Andy C. Wei ,  Jeong Soo Kim ,  Francis M. Tambwe

    IPC: H01L21/76 ,  H01L21/762 ,  H01L23/544 ,  H01L21/308 ,  H01L27/088

    CPC classification number: H01L23/544 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.

    Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的翅片结构，其中鳍结构限定对准/覆盖标记沟槽的一部分，其中将形成至少一部分对准/覆盖标记，形成 至少一层绝缘材料，其过度填充对准/覆盖标记沟槽，并且移除位于多个翅片的上表面上方的绝缘材料层的多余部分，从而限定定位/重叠标记的至少一部分 对准/重叠标记沟槽。 本文公开的装置包括形成在半导体衬底中的多个间隔开的翅片结构，以便部分地限定对准/覆盖标记沟槽，对准/覆盖标记仅由位于对准/覆盖标记内的至少一个绝缘材料组成 沟槽，以及形成在衬底中和上方的多个FinFET半导体器件。

    METHOD FOR FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT WITH A LITHO-ETCH, LITHO-ETCH PROCESS FOR ETCHING TRENCHES
    2.
    发明申请
    METHOD FOR FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT WITH A LITHO-ETCH, LITHO-ETCH PROCESS FOR ETCHING TRENCHES 有权
    用LITHO-ETCH制造半导体集成电路的方法，用于蚀刻电镀的LITHO蚀刻工艺

    公开(公告)号：US20140235055A1

    公开(公告)日：2014-08-21

    申请号：US13767993

    申请日：2013-02-15

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

    IPC: H01L21/308

    CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

    Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

    Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。

    METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES AND THE RESULTING ALIGNMENT/OVERLAY MARK
    5.
    发明申请
    METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES AND THE RESULTING ALIGNMENT/OVERLAY MARK 有权
    在使用FINFET器件和结果对齐/覆盖标记的集成电路产品上形成对齐标记和覆盖标记的方法

    公开(公告)号：US20140264631A1

    公开(公告)日：2014-09-18

    申请号：US13834608

    申请日：2013-03-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Andy C. Wei ,  Jeong Soo Kim ,  Francis M. Tambwe

    IPC: H01L21/762 ,  H01L21/3105 ,  H01L27/088

    CPC classification number: H01L23/544 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.

    Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的翅片结构，其中鳍结构限定对准/覆盖标记沟槽的一部分，其中将形成至少一部分对准/覆盖标记，形成 至少一层绝缘材料，其过度填充对准/覆盖标记沟槽，并且移除位于多个翅片的上表面上方的绝缘材料层的多余部分，从而限定定位/重叠标记的至少一部分 对准/重叠标记沟槽。 本文公开的装置包括形成在半导体衬底中的多个间隔开的翅片结构，以便部分地限定对准/覆盖标记沟槽，对准/覆盖标记仅由位于对准/覆盖标记内的至少一个绝缘材料组成 沟槽，以及形成在衬底中和上方的多个FinFET半导体器件。

    METHODS OF AVOIDING SHADOWING WHEN FORMING SOURCE/DRAIN IMPLANT REGIONS ON 3D SEMICONDUCTOR DEVICES
    6.
    发明申请
    METHODS OF AVOIDING SHADOWING WHEN FORMING SOURCE/DRAIN IMPLANT REGIONS ON 3D SEMICONDUCTOR DEVICES 审中-公开
    在三维半导体器件形成源/漏侵入区域时防止遮蔽的方法

    公开(公告)号：US20140113420A1

    公开(公告)日：2014-04-24

    申请号：US13658928

    申请日：2012-10-24

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Vidmantas Sargunas ,  Yayi Wei ,  Jeong Soo Kim ,  Seung Y. Kim

    IPC: H01L21/8238

    CPC classification number: H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66803

    Abstract: One illustrative method disclosed herein includes forming a patterned photoresist implant mask that has an opening that is defined, at least partially, by a plurality of non-vertical sidewalls, wherein the implant mask covers one of an N-type FinFET or P-type FinFET device, while the other of the N-type FinFET or P-type FinFET device is exposed by the opening in the patterned photoresist implant mask, and performing at least one source/drain implant process through the opening in the patterned photoresist implant mask to form a doped source/drain implant region in at least one fin of the FinFET device exposed by the opening in the patterned photoresist implant mask.

    Abstract translation: 本文公开的一种说明性方法包括形成具有至少部分由多个非垂直侧壁限定的开口的图案化光刻胶注入掩模，其中所述注入掩模覆盖N型FinFET或P型FinFET 器件，而N型FinFET或P型FinFET器件中的另一个由图案化的光致抗蚀剂注入掩模中的开口暴露，并且通过图案化的光致抗蚀剂植入掩模中的开口执行至少一个源极/漏极注入工艺以形成 在由图案化的光致抗蚀剂植入掩模中的开口暴露的FinFET器件的至少一个鳍中的掺杂源极/漏极注入区域。

    Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches
    7.
    发明授权
    Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches 有权
    用于蚀刻沟槽的用于蚀刻光刻蚀工艺的半导体集成电路的制造方法

    公开(公告)号：US09171735B2

    公开(公告)日：2015-10-27

    申请号：US13767993

    申请日：2013-02-15

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

    IPC: H01L21/308 ,  G03F7/00

    CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

    Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

    Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。

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