公开(公告)号：US10056458B2

公开(公告)日：2018-08-21

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho Maeng ,  Andy Wei ,  Anthony Ozzello ,  Bharat Krishnan ,  Guillaume Bouche ,  Haifeng Sheng ,  Haigou Huang ,  Huang Liu ,  Huy M. Cao ,  Ja-Hyung Han ,  SangWoo Lim ,  Kenneth A. Bates ,  Shyam Pal ,  Xintuo Dai ,  Jinping Liu

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US10181420B2

公开(公告)日：2019-01-15

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Michael Permana ,  Guillaume Bouche ,  Andy Wei ,  Mark Zaleski ,  Anbu Selvam K M Mahalingam ,  Craig Michael Child, Jr. ,  Roderick Alan Augur ,  Shyam Pal ,  Linus Jang ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20180061699A1

公开(公告)日：2018-03-01

申请号：US15253097

申请日：2016-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shyam Pal ,  Granger Lobb ,  Aleksandra Clancy

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76877

Abstract: A method includes forming a stack of hard mask layers above a process layer. The stack includes first, second and third hard mask layers. The third hard mask layer is patterned to define therein a first mask element and to expose portions of the second hard mask layer. The second hard mask layer is patterned to define therein a second mask element below the first mask element and a third mask element, and to expose portions of the first hard mask layer. The first hard mask layer is patterned to define therein a fourth mask element below the second mask element, a fifth mask element below the third mask element, and a sixth mask element, and to expose portions of the process layer. The process layer is etched to remove portions of the process layer not covered by the first hard mask layer.

公开(公告)号：US20140235055A1

公开(公告)日：2014-08-21

申请号：US13767993

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

IPC: H01L21/308

CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。

公开(公告)号：US10026645B2

公开(公告)日：2018-07-17

申请号：US15253097

申请日：2016-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shyam Pal ,  Granger Lobb ,  Aleksandra Clancy

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311

Abstract: A method includes forming a stack of hard mask layers above a process layer. The stack includes first, second and third hard mask layers. The third hard mask layer is patterned to define therein a first mask element and to expose portions of the second hard mask layer. The second hard mask layer is patterned to define therein a second mask element below the first mask element and a third mask element, and to expose portions of the first hard mask layer. The first hard mask layer is patterned to define therein a fourth mask element below the second mask element, a fifth mask element below the third mask element, and a sixth mask element, and to expose portions of the process layer. The process layer is etched to remove portions of the process layer not covered by the first hard mask layer.

公开(公告)号：US09171735B2

公开(公告)日：2015-10-27

申请号：US13767993

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

IPC: H01L21/308 ,  G03F7/00

CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。