公开(公告)号：US09991167B2

公开(公告)日：2018-06-05

申请号：US15085077

申请日：2016-03-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arvind Kumar ,  Murshed M. Chowdhury ,  Brian J. Greene ,  Chung-Hsun Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/381

Abstract: Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

公开(公告)号：US20170287829A1

公开(公告)日：2017-10-05

申请号：US15085077

申请日：2016-03-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arvind Kumar ,  Murshed M. Chowdhury ,  Brian J. Greene ,  Chung-Hsun Lin

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/08 ,  H01L23/535 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161

CPC classification number: H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/381

Abstract: Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

公开(公告)号：US09748235B2

公开(公告)日：2017-08-29

申请号：US15013169

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aritra Dasgupta ,  Benjamin G. Moser ,  Mohammad Hasanuzzaman ,  Murshed M. Chowdhury ,  Shahrukh A. Khan ,  Shafaat Ahmed ,  Joyeeta Nag

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.

公开(公告)号：US20170221889A1

公开(公告)日：2017-08-03

申请号：US15013169

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aritra Dasgupta ,  Benjamin G. Moser ,  Mohammad Hasanuzzaman ,  Murshed M. Chowdhury ,  Shahrukh A. Khan ,  Shafaat Ahmed ,  Joyeeta Nag

IPC: H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.

公开(公告)号：US09431485B2

公开(公告)日：2016-08-30

申请号：US14580274

申请日：2014-12-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat Ahmed ,  Murshed M. Chowdhury ,  Aritra Dasgupta ,  Mohammad Hasanuzzaman ,  Shahrukh Akbar Khan ,  Joyeeta Nag

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1045 ,  H01L21/265 ,  H01L21/26513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a finFET structure having an ion implanted intermediate region next to the channel region of a finFET gate. The intermediate region is formed in a manner to reduce or eliminate migration of the dopant to undoped regions of the finFET thus forming abrupt finFET junction.

Abstract translation: 一种在finFET栅极的沟道区域旁边形成离子注入中间区域的finFET结构的方法。 中间区域以减少或消除掺杂剂向finFET的未掺杂区域迁移的方式形成，从而形成突变的finFET结。