公开(公告)号：US09741581B2

公开(公告)日：2017-08-22

申请号：US14992391

申请日：2016-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunit S. Mahajan ,  Parul Dhagat ,  Anne C. Friedman ,  Timothy A. Brunner ,  Shahrukh A. Khan

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/3081 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657

Abstract: A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask including a first area having a pattern for forming a plurality of openings and an adjacent second area free of openings, and the hard mask includes a tensile stress therein. The hard mask may be used to form the plurality of openings in the substrate. Partially eroding the hard mask leaves the substrate with the plurality of openings therein and a substantially planar surface, having diminished buckling.

公开(公告)号：US09806161B1

公开(公告)日：2017-10-31

申请号：US15092910

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shahrukh A. Khan ,  Unoh Kwon ,  Shahab Siddiqui ,  Sean M. Polvino ,  Joseph F. Shepard, Jr.

IPC: H01L29/423 ,  H01L21/311 ,  H01L29/51 ,  H01L21/033 ,  H01L21/84 ,  H01L21/027 ,  H01L21/8234 ,  H01L27/12

CPC classification number: H01L29/42364 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/28202 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1207 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

公开(公告)号：US20170294519A1

公开(公告)日：2017-10-12

申请号：US15092910

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shahrukh A. Khan ,  Unoh Kwon ,  Shahab Siddiqui ,  Sean M. Polvino ,  Joseph F. Shepard, JR.

IPC: H01L29/423 ,  H01L21/027 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/12 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L29/42364 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/28202 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1207 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

公开(公告)号：US09685334B1

公开(公告)日：2017-06-20

申请号：US15134917

申请日：2016-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yue Ke ,  Mohammad Hasanuzzaman ,  Benjamin G. Moser ,  Shahrukh A. Khan ,  Sean M. Polvino

IPC: H01L21/225 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/2254 ,  H01L21/02378 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/2257 ,  H01L29/66795

Abstract: Methods of forming a semiconductor fin and methods for controlling dopant diffusion to a semiconductor fin are disclosed herein. The methods provide alternative ways to incorporate a carbon dopant into the fin to later control out-diffusion of dopants from a dopant-including epitaxial layer. One method includes depositing a carbon-containing layer over a portion of the fin adjacent to the gate and annealing to diffuse carbon from the carbon-containing layer into at least the portion of the semiconductor fin. This method can be applied to SOI or bulk semiconductor substrates. Another method includes epitaxially growing a carbon dopant containing semiconductor layer for later use in forming the fin.

公开(公告)号：US20170170016A1

公开(公告)日：2017-06-15

申请号：US14967755

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Woo-Hyeong Lee ,  Jujin An ,  Shahrukh A. Khan ,  Rosa A. Orozco-Teran ,  Oluwafemi O. Ogunsola ,  William K. Henson ,  Scott R. Stiffler

IPC: H01L21/033 ,  H01L21/8238 ,  H01L21/027

CPC classification number: H01L21/823871 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/743 ,  H01L21/76816 ,  H01L21/76898 ,  H01L23/485

Abstract: Methods for multiple patterning a substrate may include: forming a hard mask including a carbonaceous layer and an oxynitride layer over the carbonaceous layer on a substrate; and forming a first pattern into the oxynitride layer and partially into the carbonaceous layer using a first soft mask positioned over the hard mask. A wet etching removes a portion of the first soft mask from the first pattern in the oxynitride layer without damaging the carbonaceous layer. Subsequently, a second pattern and a third pattern are formed into the hard mask, creating a multiple pattern in the hard mask. The multiple pattern may be etched into the substrate, followed by removing any remaining portion of the hard mask.

公开(公告)号：US09748235B2

公开(公告)日：2017-08-29

申请号：US15013169

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aritra Dasgupta ,  Benjamin G. Moser ,  Mohammad Hasanuzzaman ,  Murshed M. Chowdhury ,  Shahrukh A. Khan ,  Shafaat Ahmed ,  Joyeeta Nag

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.

公开(公告)号：US20170221889A1

公开(公告)日：2017-08-03

申请号：US15013169

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aritra Dasgupta ,  Benjamin G. Moser ,  Mohammad Hasanuzzaman ,  Murshed M. Chowdhury ,  Shahrukh A. Khan ,  Shafaat Ahmed ,  Joyeeta Nag

IPC: H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.

公开(公告)号：US20170200614A1

公开(公告)日：2017-07-13

申请号：US14992391

申请日：2016-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunit S. Mahajan ,  Parul Dhagat ,  Anne C. Friedman ,  Timothy A. Brunner ,  Shahrukh A. Khan

IPC: H01L21/308 ,  H01L29/06 ,  H01L27/088 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L21/3081 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657

Abstract: A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask including a first area having a pattern for forming a plurality of openings and an adjacent second area free of openings, and the hard mask includes a tensile stress therein. The hard mask may be used to form the plurality of openings in the substrate. Partially eroding the hard mask leaves the substrate with the plurality of openings therein and a substantially planar surface, having diminished buckling.