公开(公告)号：US09431485B2

公开(公告)日：2016-08-30

申请号：US14580274

申请日：2014-12-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat Ahmed ,  Murshed M. Chowdhury ,  Aritra Dasgupta ,  Mohammad Hasanuzzaman ,  Shahrukh Akbar Khan ,  Joyeeta Nag

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1045 ,  H01L21/265 ,  H01L21/26513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a finFET structure having an ion implanted intermediate region next to the channel region of a finFET gate. The intermediate region is formed in a manner to reduce or eliminate migration of the dopant to undoped regions of the finFET thus forming abrupt finFET junction.

Abstract translation: 一种在finFET栅极的沟道区域旁边形成离子注入中间区域的finFET结构的方法。 中间区域以减少或消除掺杂剂向finFET的未掺杂区域迁移的方式形成，从而形成突变的finFET结。

公开(公告)号：US20190035739A1

公开(公告)日：2019-01-31

申请号：US15661029

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang Fang ,  Haigou Huang ,  Shafaat Ahmed ,  Changhong Wu ,  Dinesh R. Koli

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L21/285 ,  H01L21/3213

Abstract: The disclosure relates to a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches with Co as a first metal such that the resulting Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer. The disclosure also relates to a Co contact module formed by the noted method.

公开(公告)号：US10109521B1

公开(公告)日：2018-10-23

申请号：US15606895

申请日：2017-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qiang Fang ,  Shafaat Ahmed ,  Changhong Wu ,  Zhiguo Sun ,  Jiehui Shu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

Abstract: A method of forming hybrid Co and Cu CA/CB contacts and the resulting device are provided. Embodiments include forming a forming a plurality of trenches through an ILD down to a substrate; forming a first metal liner on side and bottom surfaces of each trench and over the ILD; annealing the first metal liner; forming a second metal liner over the first metal liner; forming a first plating layer over a portion of the second metal liner in each trench; forming a second plating layer over the second metal liner and first plating layer in a remaining portion of each trench, the first and second plating layers being different materials; and planarizing the second plating layer and the second and first metal liners down to the ILD.

公开(公告)号：US10020260B1

公开(公告)日：2018-07-10

申请号：US15388530

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat Ahmed ,  Benjamin G. Moser ,  Vimal Kumar Kamineni ,  Dinesh Koli ,  Vishal Chhabra

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/265 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.

公开(公告)号：US09899324B1

公开(公告)日：2018-02-20

申请号：US15362499

申请日：2016-11-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shafaat Ahmed ,  Sadanand Vinayak Despande ,  Atsushi Ogino

IPC: H01L23/528 ,  H01L23/544 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76879 ,  H01L23/53238 ,  H01L23/562 ,  H01L23/585 ,  H01L2223/5446

Abstract: A method includes providing a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, and forming a metallic structure on the semiconductor substrate to serve as a bus bar for the printed circuits and/or semiconductor devices. A semiconductor structure is realized with the method, the semiconductor structure including a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, a metallic structure on the semiconductor substrate serving as a bus bar for the printed circuits and/or semiconductor devices, and printed circuits and/or semiconductor devices in the semiconductor areas.

公开(公告)号：US09293632B2

公开(公告)日：2016-03-22

申请号：US14030019

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat Ahmed ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Raman Vaidyanathan

IPC: H01L31/18 ,  H01L21/02

CPC classification number: H01L31/1876 ,  C25D17/001 ,  H01L21/02425 ,  H01L21/02491 ,  H01L21/02521 ,  H01L21/02568 ,  H01L21/02614 ,  H01L31/0322 ,  H01L31/0749 ,  H01L31/18 ,  H01L31/206 ,  Y02E10/541 ,  Y02P70/521

Abstract: In one aspect, a method for fabricating a thin film solar cell includes the following steps. A first absorber material is deposited as a layer A on a substrate while applying pressure to the substrate/layer A. A second absorber material is deposited as a layer B on layer A while applying pressure to the substrate/layer B. A third absorber material is deposited as a layer C on layer B while applying pressure to the substrate/layer C. A fourth absorber material is deposited as a layer D on layer C while applying pressure to the substrate/layer D. The first absorber material comprises copper, the second absorber material comprises indium, the third absorber material comprises gallium, and the fourth absorber material comprises one or more of sulfur and selenium, and wherein by way of performing the steps of claim 1 a chalcogenide absorber layer is formed on the substrate.

Abstract translation: 一方面，制造薄膜太阳能电池的方法包括以下步骤。 第一吸收材料作为层A沉积在衬底上，同时向衬底/层A施加压力。第二吸收剂材料作为层B沉积在层A上，同时向衬底/层B施加压力。第三吸收材料 在层B上沉积为层C，同时向衬底/层C施加压力。第四吸收材料作为层C沉积在层C上，同时向衬底/层D施加压力。第一吸收材料包括铜， 第二吸收体材料包括铟，第三吸收体材料包括镓，第四吸收体材料包括硫和硒中的一种或多种，​​并且其中通过执行权利要求1的步骤，在衬底上形成硫族化物吸收层。

公开(公告)号：US20160047058A1

公开(公告)日：2016-02-18

申请号：US14928088

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc

Inventor： Shafaat Ahmed ,  Michael P. Chudzik ,  Lubomyr T. Romankiw

IPC: C25D21/04 ,  C25D5/08 ,  C25D17/00 ,  C25D21/10 ,  C25D5/04 ,  C25D5/20

CPC classification number: C25D21/04 ,  C25D5/04 ,  C25D5/08 ,  C25D5/20 ,  C25D7/123 ,  C25D17/001 ,  C25D17/008 ,  C25D21/10

Abstract: An electroplating apparatus includes an anode configured to electrically communicate with an electrical voltage and an electrolyte solution. A cathode module includes a cathode that is configured to electrically communicate with a ground potential and the electrolyte solution. The cathode module further includes a wafer in electrical communication with the cathode. The wafer is configured to receive metal ions from the anode in response to current flowing through the anode via electrodeposition. The electroplating apparatus further includes at least one agitating device interposed between the wafer and the anode. The agitating device is configured to apply a force to gas bubbles adhering to a surface of the wafer facing the agitating device.

Abstract translation: 电镀设备包括被配置为与电压和电解质溶液电连通的阳极。 阴极模块包括被配置为与地电位和电解质溶液电连通的阴极。 阴极模块还包括与阴极电连通的晶片。 晶片被配置为响应于电流通过电沉积而流过阳极而从阳极接收金属离子。 电镀装置还包括插入在晶片和阳极之间的至少一个搅拌装置。 搅拌装置构造成对粘附到面向搅拌装置的晶片表面的气泡施加力。

公开(公告)号：US10340183B1

公开(公告)日：2019-07-02

申请号：US15860318

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang Fang ,  Shafaat Ahmed ,  Zhiguo Sun ,  Jiehui Shu ,  Dinesh R. Koli ,  Wei-Tsu Tseng

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cobalt plated via integration scheme and methods of manufacture. The structure includes: a via structure composed of cobalt material; and a wiring structure above the via structure. The wiring structure is lined with a barrier liner and the cobalt material and filled with conductive material.

公开(公告)号：US10262942B2

公开(公告)日：2019-04-16

申请号：US15661029

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang Fang ,  Haigou Huang ,  Shafaat Ahmed ,  Changhong Wu ,  Dinesh R. Koli

IPC: H01L21/4763 ,  H01L23/12 ,  H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L21/285 ,  H01L21/3213

Abstract: The disclosure relates to a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches with Co as a first metal such that the resulting Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer. The disclosure also relates to a Co contact module formed by the noted method.

公开(公告)号：US09748235B2

公开(公告)日：2017-08-29

申请号：US15013169

申请日：2016-02-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aritra Dasgupta ,  Benjamin G. Moser ,  Mohammad Hasanuzzaman ,  Murshed M. Chowdhury ,  Shahrukh A. Khan ,  Shafaat Ahmed ,  Joyeeta Nag

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.