公开(公告)号：US09966457B2

公开(公告)日：2018-05-08

申请号：US15073740

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/321 ,  H01L21/306 ,  H01L21/324 ,  H01L21/768

CPC classification number: H01L29/66818 ,  H01L21/30604 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US09502408B2

公开(公告)日：2016-11-22

申请号：US14079733

申请日：2013-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate to a first thickness, forming a sacrificial gate stack on portions of the fins, forming source drain junctions using ion implantation, forming a dielectric layer on the substrate, removing the sacrificial gate stack to expose the portions of the fins, thinning the exposed portions of the fins to a second thickness less than the first thickness, and forming a gate stack on the thinned exposed portions of the fins to replace the removed sacrificial gate stack.

Abstract translation: 一种用于制造鳍状场效应晶体管（FinFET）器件的方法，包括在衬底上形成多个翅片至第一厚度，在鳍片的部分上形成牺牲栅极叠层，使用离子注入形成源漏极结，形成 电介质层，去除牺牲栅极堆叠以暴露散热片的部分，将散热片的暴露部分减薄到小于第一厚度的第二厚度，以及在散热片的变薄的暴露部分上形成栅极堆叠 更换去除的牺牲栅极堆叠。

公开(公告)号：US09276118B2

公开(公告)日：2016-03-01

申请号：US14640851

申请日：2015-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other.

Abstract translation: 一种用于制造鳍状场效应晶体管（FinFET）器件的方法，包括在衬底上形成多个鳍片，在鳍片的部分上形成多个栅极区域，其中栅极区域彼此间隔开，形成间隔物 在每个相应的栅极区域上，在每个鳍片上外延生长第一外延区域，在相邻鳍片之间的第一外延区域合并之前停止第一外延区域的生长，在包括鳍片的衬底上形成介电层，并且第一外延 在相邻栅极区之间的一个或多个部分处从所述鳍片去除所述电介质层和所述第一外延区域，以形成一个或多个接触区域沟槽，以及在所述一个或多个接触区域中的所述鳍片上外延生长第二外延区域 沟槽，其中相邻鳍片上的第二外延区域彼此合并。

公开(公告)号：US20180190797A1

公开(公告)日：2018-07-05

申请号：US15911415

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/306 ,  H01L21/324 ,  H01L21/321 ,  H01L21/768

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US10680085B2

公开(公告)日：2020-06-09

申请号：US15911415

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/321 ,  H01L21/306 ,  H01L21/324 ,  H01L21/768

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US20170271483A1

公开(公告)日：2017-09-21

申请号：US15073740

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/768 ,  H01L21/306 ,  H01L21/324 ,  H01L29/78 ,  H01L21/321

CPC classification number: H01L29/66818 ,  H01L21/30604 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US09505611B1

公开(公告)日：2016-11-29

申请号：US14814083

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Fei Liu ,  Qiqing C. Ouyang ,  Keith Kwong Hon Wong

IPC: B81C1/00 ,  H01L29/66 ,  B81B7/00

CPC classification number: B81C1/00246 ,  B81B7/008 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81C2201/0132 ,  B81C2201/056 ,  B81C2203/0714 ,  H01L27/0617 ,  H01L29/66545

Abstract: Semiconductor devices and methods are provided for integrally forming electromechanical devices (e.g. MEMS or NEMS devices) with CMOS devices in a FEOL (front-end-of-line) structure as part of a replacement metal gate process flow. For example, a method includes forming an electromechanical device in a first device region of a substrate and forming a transistor device in a second device region of the substrate. The electromechanical device includes a sacrificial anchor structure and a sacrificial cantilever structure formed of a sacrificial material. The transistor device includes a sacrificial gate electrode structure formed of the sacrificial material. A replacement metal gate process is performed to replace the sacrificial gate electrode structure of the transistor device with a metallic gate electrode, and to replace the sacrificial anchor structure and the sacrificial cantilever structure with a metallic anchor structure and a metallic cantilever structure. A release process is performed to release the metallic cantilever structure.

Abstract translation: 提供半导体器件和方法，用于在作为替代金属栅极工艺流程的一部分的FEOL（前端线）结构中与CMOS器件一体地形成机电装置（例如MEMS或NEMS器件）。 例如，一种方法包括在衬底的第一器件区域中形成机电器件，并在衬底的第二器件区域中形成晶体管器件。 机电装置包括牺牲锚结构和由牺牲材料形成的牺牲悬臂结构。 晶体管器件包括由牺牲材料形成的牺牲栅电极结构。 执行替换金属栅极处理以用金属栅极电极代替晶体管器件的牺牲栅电极结构，并用金属锚结构和金属悬臂结构代替牺牲锚结构和牺牲悬臂结构。 执行释放过程以释放金属悬臂结构。