公开(公告)号：US09484359B2

公开(公告)日：2016-11-01

申请号：US14696736

申请日：2015-04-27

申请人： GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Bruce B Doris ,  Pranita Kerber ,  Ali Khakifirooz

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786 ,  H01L21/762 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/76267 ,  H01L21/84 ,  H01L29/45 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/78648

摘要： An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.

公开(公告)号：US09337259B2

公开(公告)日：2016-05-10

申请号：US14154438

申请日：2014-01-14

申请人： GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kerber ,  Ali Khakifirooz ,  Balasubramanian Pranatharthiharan

IPC分类号： H01L29/06 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

摘要： A structure to improve ETSOI MOSFET devices includes a wafer having regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in the hole.

摘要翻译： 改进ETSOI MOSFET器件的结构包括具有至少覆盖在第二半导体层上的氧化物层上的第一半导体层的区域的晶片。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔没有完全着陆，至少部分地延伸到STI中，并且绝缘材料沉积在孔中。

公开(公告)号：US09240497B2

公开(公告)日：2016-01-19

申请号：US14167499

申请日：2014-01-29

申请人： GLOBALFOUNDRIES INC.

发明人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber

IPC分类号： H01L21/338 ,  H01L29/812 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808

CPC分类号： H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

摘要： A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

公开(公告)号：US09966457B2

公开(公告)日：2018-05-08

申请号：US15073740

申请日：2016-03-18

申请人： GLOBALFOUNDRIES INC.

发明人： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/321 ,  H01L21/306 ,  H01L21/324 ,  H01L21/768

CPC分类号： H01L29/66818 ,  H01L21/30604 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US09502408B2

公开(公告)日：2016-11-22

申请号：US14079733

申请日：2013-11-14

申请人： GLOBALFOUNDRIES INC.

发明人： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L27/0886 ,  H01L21/823431

摘要： A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate to a first thickness, forming a sacrificial gate stack on portions of the fins, forming source drain junctions using ion implantation, forming a dielectric layer on the substrate, removing the sacrificial gate stack to expose the portions of the fins, thinning the exposed portions of the fins to a second thickness less than the first thickness, and forming a gate stack on the thinned exposed portions of the fins to replace the removed sacrificial gate stack.

摘要翻译： 一种用于制造鳍状场效应晶体管（FinFET）器件的方法，包括在衬底上形成多个翅片至第一厚度，在鳍片的部分上形成牺牲栅极叠层，使用离子注入形成源漏极结，形成 电介质层，去除牺牲栅极堆叠以暴露散热片的部分，将散热片的暴露部分减薄到小于第一厚度的第二厚度，以及在散热片的变薄的暴露部分上形成栅极堆叠 更换去除的牺牲栅极堆叠。

公开(公告)号：US09356119B2

公开(公告)日：2016-05-31

申请号：US13770545

申请日：2013-02-19

申请人： GLOBALFOUNDRIES INC.

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber

IPC分类号： H01L29/66 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L23/485 ,  H01L29/165

CPC分类号： H01L29/66477 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.

公开(公告)号：US09356019B2

公开(公告)日：2016-05-31

申请号：US14700147

申请日：2015-04-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber ,  Ghavam G. Shahidi

IPC分类号： H01L29/868 ,  H01L27/06 ,  H01L29/08 ,  H01L29/861

CPC分类号： H01L27/0629 ,  H01L29/0847 ,  H01L29/8611 ,  H01L29/868

摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

公开(公告)号：US09276118B2

公开(公告)日：2016-03-01

申请号：US14640851

申请日：2015-03-06

申请人： GLOBALFOUNDRIES INC.

发明人： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC分类号： H01L27/01 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/785 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7853

摘要： A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other.

摘要翻译： 一种用于制造鳍状场效应晶体管（FinFET）器件的方法，包括在衬底上形成多个鳍片，在鳍片的部分上形成多个栅极区域，其中栅极区域彼此间隔开，形成间隔物 在每个相应的栅极区域上，在每个鳍片上外延生长第一外延区域，在相邻鳍片之间的第一外延区域合并之前停止第一外延区域的生长，在包括鳍片的衬底上形成介电层，并且第一外延 在相邻栅极区之间的一个或多个部分处从所述鳍片去除所述电介质层和所述第一外延区域，以形成一个或多个接触区域沟槽，以及在所述一个或多个接触区域中的所述鳍片上外延生长第二外延区域 沟槽，其中相邻鳍片上的第二外延区域彼此合并。

公开(公告)号：US10680085B2

公开(公告)日：2020-06-09

申请号：US15911415

申请日：2018-03-05

申请人： GLOBALFOUNDRIES INC.

发明人： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/321 ,  H01L21/306 ,  H01L21/324 ,  H01L21/768

摘要： Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US20170271483A1

公开(公告)日：2017-09-21

申请号：US15073740

申请日：2016-03-18

申请人： GLOBALFOUNDRIES INC.

发明人： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L21/768 ,  H01L21/306 ,  H01L21/324 ,  H01L29/78 ,  H01L21/321

CPC分类号： H01L29/66818 ,  H01L21/30604 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.