公开(公告)号：US20210074577A1

公开(公告)日：2021-03-11

申请号：US17086925

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US10903316B2

公开(公告)日：2021-01-26

申请号：US16575675

申请日：2019-09-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli

IPC: H01L21/764 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US20200272880A1

公开(公告)日：2020-08-27

申请号：US16283887

申请日：2019-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Siva P. Adusumilli ,  Ruilong Xie ,  Julien Frougier

IPC: G06N3/04 ,  H01L27/24 ,  H01L29/872 ,  H01L45/00

Abstract: Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

公开(公告)号：US10446643B2

公开(公告)日：2019-10-15

申请号：US15876727

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Laura J. Schutz ,  Cameron E. Luce

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

公开(公告)号：US20190287847A1

公开(公告)日：2019-09-19

申请号：US15924444

申请日：2018-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/48

Abstract: Structures with a cavity beneath semiconductor devices and methods associated with forming such substrates. A first semiconductor layer is formed on a first side of a first handle wafer. A device structure is formed that is arranged at least in part in the first semiconductor layer. After forming the device structure, the first handle wafer is thinned from a second side of the first handle wafer opposite to the first side of the first handle wafer in order to form a second semiconductor layer from the first handle wafer. After thinning the first handle wafer, a cavity is formed in the second semiconductor layer. The cavity is arranged in the second semiconductor layer beneath the device structure. A second handle wafer is attached to the second semiconductor layer to close the cavity.

公开(公告)号：US20190172846A1

公开(公告)日：2019-06-06

申请号：US16258714

申请日：2019-01-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/12 ,  H01L49/02 ,  H01L21/762 ,  H01L29/06 ,  H01L27/06 ,  H01L29/45 ,  H01L29/08 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/02

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US10770374B2

公开(公告)日：2020-09-08

申请号：US16255505

申请日：2019-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  G02B6/12 ,  G02B6/136 ,  G02B6/30 ,  G02B6/132

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to through-silicon vias (TSV) for heterogeneous integration of semiconductor device structures and methods of manufacture. The structure includes: a plurality of cavity structures provided in a single substrate; at least one optical device provided on two sides of the single substrate and between the plurality of cavity structures; and a through wafer optical via extending through the substrate, between the plurality of cavity structures and which exposes a backside of the at least one optical device.

公开(公告)号：US10580893B2

公开(公告)日：2020-03-03

申请号：US15947364

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L21/324 ,  H01L23/10 ,  H01L29/06 ,  H01L29/10 ,  H01L27/12 ,  H01L21/02 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.

公开(公告)号：US10461152B2

公开(公告)日：2019-10-29

申请号：US15645655

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli

IPC: H01L21/764 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/78

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US10163679B1

公开(公告)日：2018-12-25

申请号：US15609742

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Richard A. Phelps ,  Anthony K. Stamper

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.