公开(公告)号：US09601428B2

公开(公告)日：2017-03-21

申请号：US14865589

申请日：2015-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Jagar Singh ,  Ashish Baraskar ,  Min-hwa Chi

IPC: H01L23/525 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/283 ,  H01L29/06 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L21/0226 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/3205 ,  H01L27/11206 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

公开(公告)号：US09275861B2

公开(公告)日：2016-03-01

申请号：US13927685

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Li Yang ,  Kejia Wang ,  Ashish Baraskar ,  Bin Yang ,  Shurong Liang

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/20

CPC classification number: H01L21/02658 ,  H01L21/02373 ,  H01L21/0243 ,  H01L21/02538 ,  H01L29/045 ,  H01L29/20

Abstract: One method disclosed herein includes forming a patterned mask layer above a surface of a semiconductor substrate, performing at least one etching process through the patterned mask layer to define a plurality of intersecting ridges that define a ridged surface in the substrate, and forming a Group III-V material on the ridged surface of the substrate. An illustrative device disclosed herein includes a Group IV substrate having a ridged surface comprised of a plurality of intersecting ridges and a Group III-V material layer positioned on the ridged surface of the Group IV substrate.

Abstract translation: 本文公开的一种方法包括在半导体衬底的表面上形成图案化掩模层，通过图案化掩模层执行至少一个蚀刻工艺，以限定在衬底中限定脊状表面的多个相交脊，并形成第III组 -V在基板的脊状表面上的材料。 本文公开的说明性装置包括具有由多个相交脊组成的脊状表面的第IV族衬底和位于第IV族衬底的脊状表面上的III-V族材料层。

公开(公告)号：US10332834B2

公开(公告)日：2019-06-25

申请号：US15421698

申请日：2017-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Jagar Singh ,  Ashish Baraskar ,  Min-hwa Chi

IPC: H01L29/06 ,  H01L23/525 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/283 ,  H01L27/112

Abstract: Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy.

公开(公告)号：US09508795B2

公开(公告)日：2016-11-29

申请号：US14613983

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Min-hwa Chi ,  Ashish Baraskar ,  Jagar Singh

IPC: H01L21/20 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/31116 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78696

Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.

Abstract translation: 提出了用于制造纳米线结构的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括例如：提供衬底并在衬底上形成翅片，使得翅片具有包括一个或多个细长的第一侧壁突出部的第一侧壁和包括一个或多个细长的第二侧壁突出部的第二侧壁， 更细长的第二侧壁突起基本上与一个或多个细长的第一侧壁突起对准; 并且用细长的第一侧壁突起和细长的第二侧壁突起各向异性地蚀刻翅片以限定一个或多个纳米线。 可以选择蚀刻剂以沿着预定义的结晶平面（例如（111）晶面）选择性地蚀刻，以形成纳米线结构。