公开(公告)号：US10734525B2

公开(公告)日：2020-08-04

申请号：US15920886

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Christopher M. Prindle ,  Nigel G. Cave

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.

公开(公告)号：US20190081145A1

公开(公告)日：2019-03-14

申请号：US15701678

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Nigel G. Cave ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A structure and method for forming sets of contact structures to source/drain regions of complimentary N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The structure including a NFET structure including a first fin positioned on a substrate and a PFET structure including a second fin positioned on the substrate, wherein a source/drain region (S/D) of the first fin and a S/D of the second fin include non-uniform openings at an uppermost surface. A method of forming non-uniformly openings in the S/Ds of the complimentary NFETs and PFETs including forming mask on the PFET to protect the structure during formation of openings in the NFET S/D. A method of forming non-uniform openings in the S/D of the complimentary NFETs and PFETs including reducing the epitaxially growth of the NFET S/D to form an opening therein.

公开(公告)号：US20150340468A1

公开(公告)日：2015-11-26

申请号：US14283721

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Min Gyu Sung ,  Jody A. Fronheiser ,  Christopher M. Prindle

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method includes forming at least one fin in a semiconductor substrate. A sacrificial gate structure is formed around a first portion of the at least one fin. Sidewall spacers are formed adjacent the sacrificial gate structure. The sacrificial gate structure and spacers expose a second portion of the at least one fin. An epitaxial material is formed on the exposed second portion. At least one process operation is performed to remove the sacrificial gate structure and thereby define a gate cavity between the spacers that exposes the first portion of the at least one fin. The first portion of the at least one fin is recessed to a first height less than a second height of the second portion of the at least one fin. A replacement gate structure is formed within the gate cavity above the recessed first portion of the at least one fin.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 在所述至少一个翅片的第一部分周围形成牺牲栅极结构。 侧壁间隔件形成在牺牲栅极结构附近。 所述牺牲栅极结构和间隔物暴露所述至少一个翅片的第二部分。 在暴露的第二部分上形成外延材料。 执行至少一个处理操作以去除牺牲栅极结构，从而在间隔件之间限定暴露至少一个鳍片的第一部分的栅极腔。 所述至少一个翅片的第一部分凹陷到小于所述至少一个翅片的第二部分的第二高度的第一高度。 在所述至少一个翅片的凹入的第一部分上方的栅极空腔内形成替换栅极结构。

公开(公告)号：US20190288117A1

公开(公告)日：2019-09-19

申请号：US15920886

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Christopher M. Prindle ,  Nigel G. Cave

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.

公开(公告)号：US20180102409A1

公开(公告)日：2018-04-12

申请号：US15833285

申请日：2017-12-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation protection layer that is positioned above the device isolation region. The FinFET device includes at least one fin, a gate structure, and a sidewall spacer, the device isolation region includes a first insulating material, and the isolation protection layer includes a material that is different from the first insulating material. A first portion of the isolation protection layer is positioned under a portion of the gate structure and under a portion of the sidewall spacer, wherein a second portion of the isolation protection layer is not positioned under the gate structure and is not positioned under the sidewall spacer, the first portion of the isolation protection layer having a thickness that is greater than a thickness of the second portion.

公开(公告)号：US10388747B1

公开(公告)日：2019-08-20

申请号：US15938510

申请日：2018-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Emilie Bourjot ,  Laertis Economikos

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L23/535 ,  H01L21/764

Abstract: One illustrative integrated circuit product disclosed herein includes a transistor device comprising a T-shaped gate structure positioned above an active region defined in a semiconducting substrate, the T-shaped portion of the gate structure comprising a relatively wider upper portion and a relatively narrower lower portion, and first and second conductive source/drain structures positioned adjacent opposite sidewalls of the T-shaped gate structure. In this example, the product also includes first and second air gaps positioned adjacent opposite sidewall of the T-shaped gate structure, wherein each of the air gaps is positioned between at least the lower portion of one of the sidewalls of the T-shaped gate structure and the adjacent conductive source/drain structure.

公开(公告)号：US09876077B1

公开(公告)日：2018-01-23

申请号：US15197944

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.

公开(公告)号：US10388770B1

公开(公告)日：2019-08-20

申请号：US15924447

申请日：2018-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Christopher M. Prindle

IPC: H01L29/41 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417

Abstract: One illustrative IC product disclosed herein includes a transistor device including a gate structure positioned above an active region, first and second conductive source/drain structures positioned adjacent opposite sidewalls of the gate structure and an insulating material positioned laterally between the gate structure and each of the first and second conductive source/drain structures. The product also includes first and second air gaps positioned adjacent opposite sidewalls of the gate structure, a gate contact structure that is positioned entirely above the active region and conductively coupled to the gate structure and a source/drain contact structure that is positioned entirely above the active region and conductively coupled to at least one of the first and second conductive source/drain structures.

公开(公告)号：US10170544B2

公开(公告)日：2019-01-01

申请号：US15833285

申请日：2017-12-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation protection layer that is positioned above the device isolation region. The FinFET device includes at least one fin, a gate structure, and a sidewall spacer, the device isolation region includes a first insulating material, and the isolation protection layer includes a material that is different from the first insulating material. A first portion of the isolation protection layer is positioned under a portion of the gate structure and under a portion of the sidewall spacer, wherein a second portion of the isolation protection layer is not positioned under the gate structure and is not positioned under the sidewall spacer, the first portion of the isolation protection layer having a thickness that is greater than a thickness of the second portion.

公开(公告)号：US20180006111A1

公开(公告)日：2018-01-04

申请号：US15197944

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.