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    DEVICE COMPRISING A PLURALITY OF FDSOI STATIC RANDOM-ACCESS MEMORY BITCELLS AND METHOD OF OPERATION THEREOF
    1.
    发明申请
    DEVICE COMPRISING A PLURALITY OF FDSOI STATIC RANDOM-ACCESS MEMORY BITCELLS AND METHOD OF OPERATION THEREOF 有权
    包含FDSOI静态随机存取存储器单元的多项设备及其操作方法

    公开(公告)号：US20160343428A1

    公开(公告)日：2016-11-24

    申请号：US14718574

    申请日：2015-05-21

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Nigel Chan ,  Germain Bossu ,  Michael Otto

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L27/1108

    Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

    Abstract translation: 一种包括以行和列排列的多个静态随机存取存储器（SRAM）位单元的器件，其中SRAM位单元包括完全耗尽的绝缘体上的硅场效应晶体管（FDSOI-FET）。 FDSOI-FET包括P沟道上拉晶体管，其中每个P沟道上拉晶体管包括一个后栅极。 该设备还包括多个位线，其中每个位线电连接到一列的SRAM位单元和多个字线，其中每个字线电连接到其中一行的SRAM位单元。 该装置还包括位线控制电路，其被配置为选择至少一个用于写入的列，其中在写入操作期间，将第一控制信号施加到至少一个列的P沟道上拉晶体管的背栅极 选择用于写入的第二控制信号和未被选择用于写入的列的P沟道上拉晶体管的后栅极。

    ALIGNMENT KEY DESIGN RULE CHECK FOR CORRECT PLACEMENT OF ABUTTING CELLS IN AN INTEGRATED CIRCUIT
    2.
    发明申请
    ALIGNMENT KEY DESIGN RULE CHECK FOR CORRECT PLACEMENT OF ABUTTING CELLS IN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20190042689A1

    公开(公告)日：2019-02-07

    申请号：US15670158

    申请日：2017-08-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nigel Chan ,  Germain Bossu

    IPC: G06F17/50

    Abstract: Methods and a computer program product are described for placing, by an electronic design tool, a first alignment key shape of a first cell and a second alignment key shape of a second cell positioned on a common edge where the first cell abuts the second cell in a physical layout design. An abutting alignment key shape is formed by placement of the first alignment key shape and the second alignment key shape in the physical layout design. The abutting alignment key shape is checked by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined shape of a correct size. The disallowed cell placement is corrected, by a designer, through substitution of an allowed cell placement to provide a corrected physical layout design for manufacture of the IC.

    Device comprising a plurality of FDSOI static random-access memory bitcells and method of operation thereof
    3.
    发明授权
    Device comprising a plurality of FDSOI static random-access memory bitcells and method of operation thereof 有权
    包括多个FDSOI静态随机存取存储器位单元的装置及其操作方法

    公开(公告)号：US09490007B1

    公开(公告)日：2016-11-08

    申请号：US14718574

    申请日：2015-05-21

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Nigel Chan ,  Germain Bossu ,  Michael Otto

    IPC: G11C11/00 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L27/1108

    Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

    Abstract translation: 一种包括以行和列排列的多个静态随机存取存储器（SRAM）位单元的器件，其中SRAM位单元包括完全耗尽的绝缘体上的硅场效应晶体管（FDSOI-FET）。 FDSOI-FET包括P沟道上拉晶体管，其中每个P沟道上拉晶体管包括一个后栅极。 该设备还包括多个位线，其中每个位线电连接到一列的SRAM位单元和多个字线，其中每个字线电连接到其中一行的SRAM位单元。 该装置还包括位线控制电路，其被配置为选择至少一个用于写入的列，其中在写入操作期间，将第一控制信号施加到至少一个列的P沟道上拉晶体管的背栅极 选择用于写入的第二控制信号和未被选择用于写入的列的P沟道上拉晶体管的后栅极。

    Alignment key design rule check for correct placement of abutting cells in an integrated circuit
    4.
    发明授权
    Alignment key design rule check for correct placement of abutting cells in an integrated circuit 有权

    公开(公告)号：US10311201B2

    公开(公告)日：2019-06-04

    申请号：US15670158

    申请日：2017-08-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nigel Chan ,  Germain Bossu

    IPC: G06F17/50

    Abstract: Methods and a computer program product are described for placing, by an electronic design tool, a first alignment key shape of a first cell and a second alignment key shape of a second cell positioned on a common edge where the first cell abuts the second cell in a physical layout design. An abutting alignment key shape is formed by placement of the first alignment key shape and the second alignment key shape in the physical layout design. The abutting alignment key shape is checked by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined shape of a correct size. The disallowed cell placement is corrected, by a designer, through substitution of an allowed cell placement to provide a corrected physical layout design for manufacture of the IC.

    IC PRODUCT WITH A NOVEL BIT CELL DESIGN AND A MEMORY ARRAY COMPRISING SUCH BIT CELLS
    6.
    发明申请
    IC PRODUCT WITH A NOVEL BIT CELL DESIGN AND A MEMORY ARRAY COMPRISING SUCH BIT CELLS 审中-公开

    公开(公告)号：US20200343248A1

    公开(公告)日：2020-10-29

    申请号：US16396916

    申请日：2019-04-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Germain Bossu ,  Nigel Chan

    IPC: H01L27/11 ,  H01L29/08 ,  H01L27/02

    Abstract: Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.

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