公开(公告)号：US10707330B2

公开(公告)日：2020-07-07

申请号：US15897570

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L21/285 ,  H01L27/12 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.

公开(公告)号：US20190043963A1

公开(公告)日：2019-02-07

申请号：US15667755

申请日：2017-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Juergen Thees ,  Clemens Fitz

IPC: H01L29/66 ,  H01L29/417

Abstract: A transistor element of a sophisticated semiconductor device includes a gate electrode structure including a metal-containing electrode material instead of the conventionally used highly doped semiconductor material. The metal-containing electrode material may be formed in an early manufacturing stage, thereby reducing overall complexity of patterning the gate electrode structure in approaches in which the gate electrode structure is formed prior to the formation of the drain and source regions. Due to the metal-containing electrode material, high conductivity at reduced parasitic capacitance may be achieved, thereby rendering the techniques of the present disclosure as highly suitable for further device scaling.

公开(公告)号：US20180047642A1

公开(公告)日：2018-02-15

申请号：US15232090

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/84 ,  H01L21/265 ,  H01L27/12 ,  H01L21/311

CPC classification number: H01L21/84 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/7834

Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

公开(公告)号：US20160079086A1

公开(公告)日：2016-03-17

申请号：US14484770

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Hans-Juergen Thees ,  Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L21/3213 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32132 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Abstract translation: 本公开提供了一种形成半导体器件的方法，包括半导体器件的栅极结构的成形，使得避免了形成硅化物之后的间隔物去除并且抑制了硅化物突出。 在本公开的一些方面，提供一种形成半导体器件的方法，其中栅极结构设置在半导体衬底的有源区上方，栅极结构包括栅电极材料和侧壁间隔物。 通过对栅极结构施加成形工艺来形成栅电极材料和侧壁间隔物中的至少一个，并且在成形栅极结构上形成硅化物部分。

公开(公告)号：US09214463B2

公开(公告)日：2015-12-15

申请号：US14326623

申请日：2014-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/76889 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/4232 ,  H01L29/4975 ,  H01L29/78

Abstract: An integrated circuit device includes a PMOS transistor and an NMOS transistor. The PMO transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the PMOS transistor, and a multi-part second sidewall spacer positioned adjacent the first sidewall spacer of the PMOS transistor, wherein the multi-part second sidewall spacer includes an upper spacer and a lower spacer. The NMOS transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the NMOS transistor, and a single second sidewall spacer positioned adjacent the first sidewall spacer of the NMOS transistor. A metal silicide region is positioned on each of the gate electrodes and on each of the at least one source/drain regions of the PMOS and the NMOS transistors.

Abstract translation: 集成电路器件包括PMOS晶体管和NMOS晶体管。 PMO晶体管包括栅极电极，至少一个源极/漏极区域，邻近PMOS晶体管的栅电极定位的第一侧壁间隔物和邻近PMOS晶体管的第一侧壁间隔物定位的多部分第二侧壁间隔物，其中 多部分第二侧壁间隔件包括上间隔件和下间隔件。 NMOS晶体管包括栅极电极，至少一个源极/漏极区域，邻近NMOS晶体管的栅电极定位的第一侧壁间隔件和邻近NMOS晶体管的第一侧壁间隔物定位的单个第二侧壁间隔物。 金属硅化物区域位于PMOS和NMOS晶体管的每个栅极电极和至少一个源极/漏极区域中的每一个上。

公开(公告)号：US10062619B2

公开(公告)日：2018-08-28

申请号：US15232090

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/311 ,  H01L21/265 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/7834

Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

公开(公告)号：US09761689B2

公开(公告)日：2017-09-12

申请号：US14484770

申请日：2014-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic Thurmer ,  Hans-Juergen Thees ,  Kai Frohberg ,  Peter Moll ,  Heike Scholz

IPC: H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/3213

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32132 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

公开(公告)号：US20140319617A1

公开(公告)日：2014-10-30

申请号：US14326623

申请日：2014-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L27/092 ,  H01L21/76889 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/4232 ,  H01L29/4975 ,  H01L29/78

Abstract: An integrated circuit device includes a PMOS transistor and an NMOS transistor. The PMO transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the PMOS transistor, and a multi-part second sidewall spacer positioned adjacent the first sidewall spacer of the PMOS transistor, wherein the multi-part second sidewall spacer includes an upper spacer and a lower spacer. The NMOS transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the NMOS transistor, and a single second sidewall spacer positioned adjacent the first sidewall spacer of the NMOS transistor. A metal silicide region is positioned on each of the gate electrodes and on each of the at least one source/drain regions of the PMOS and the NMOS transistors.

Abstract translation: 集成电路器件包括PMOS晶体管和NMOS晶体管。 PMO晶体管包括栅极电极，至少一个源极/漏极区域，邻近PMOS晶体管的栅电极定位的第一侧壁间隔物和邻近PMOS晶体管的第一侧壁间隔物定位的多部分第二侧壁间隔物，其中 多部分第二侧壁间隔件包括上间隔件和下间隔件。 NMOS晶体管包括栅极电极，至少一个源极/漏极区域，邻近NMOS晶体管的栅电极定位的第一侧壁间隔件和邻近NMOS晶体管的第一侧壁间隔物定位的单个第二侧壁间隔物。 金属硅化物区域位于PMOS和NMOS晶体管的每个栅极电极和至少一个源极/漏极区域中的每一个上。

公开(公告)号：US20140191332A1

公开(公告)日：2014-07-10

申请号：US14208423

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Stephan Kronholz ,  Peter Javorka

IPC: H01L27/088 ,  H01L29/10 ,  H01L27/108

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L27/108 ,  H01L27/10894 ,  H01L29/1033

Abstract: Disclosed herein is a device that includes a first PFET transistor formed in and above a first active region of a semiconducting substrate, a second PFET transistor formed in and above a second active region of the semiconducting substrate, wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different.

Abstract translation: 本文公开了一种器件，其包括形成在半导体衬底的第一有源区中和上方的第一PFET晶体管，形成在半导体衬底的第二有源区中和之上的第二PFET晶体管，其中， 第一和第二沟道半导体材料或第一和第二沟道半导体材料中的锗浓度不同。

公开(公告)号：US20190252522A1

公开(公告)日：2019-08-15

申请号：US15897570

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars ,  Elliot John Smith

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L27/12 ,  H01L21/306 ,  H01L21/285

Abstract: A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.