公开(公告)号：US20180286967A1

公开(公告)日：2018-10-04

申请号：US15997368

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Jer-Hueih(James) CHEN ,  Cuiqin XU ,  Padmaja NAGAIAH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/28 ,  H01L29/06 ,  H01L21/762 ,  H01L29/08 ,  H01L21/308

Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

公开(公告)号：US20160343607A1

公开(公告)日：2016-11-24

申请号：US14716938

申请日：2015-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Jer-Hueih(James) CHEN ,  Cuiqin XU ,  Padmaja NAGAIAH

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28 ,  H01L29/165 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/28008 ,  H01L21/3083 ,  H01L21/76232 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

Abstract translation: 形成在Si衬底的部分上延伸的自对准STI区域的方法，以便能够随后在不使用光刻掩模的情况下形成外延生长的嵌入式S / D区域，并且提供所得到的器件。 实施例包括在Si衬底上形成具有横向分开的开口的STI蚀刻掩模; 通过开口将浅沟槽形成Si衬底; 在浅沟槽和开口的相对侧壁上形成第一至第四氧化物间隔物; 在第一和第二氧化物间隔物之间​​以及第三和第四氧化物间隔物之间​​形成深的STI沟槽，进入Si衬底; 在所述第一至第四氧化物间隔物和所述STI蚀刻掩模的一部分上形成STI氧化物层，所述STI氧化物层填充所述深STI沟槽; 并且将STI氧化物层平坦化到STI蚀刻掩模的部分。

公开(公告)号：US20150249136A1

公开(公告)日：2015-09-03

申请号：US14195330

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Feng ZHOU ,  Tien-Ying LUO ,  Haiting WANG ,  Padmaja NAGAIAH ,  Jean-Baptiste LALOE ,  Isabelle Pauline FERAIN ,  Yong Meng LEE

IPC: H01L29/40 ,  H01L21/311 ,  H01L29/51

CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/3247 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545

Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.

Abstract translation: 提供了一种用于制造半导体器件的改进方法。 该方法包括：在基底上沉积电介质层; 在所述电介质层上沉积第一盖层; 在所述电介质层上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积虚拟盖层以形成部分栅极结构。 还提供了部分形成的半导体器件。 部分形成的半导体器件包括：衬底; 基底上的电介质层; 介电层上的第一盖层; 介电层上的蚀刻停止层; 以及形成部分栅极结构的蚀刻停止层上的虚设盖层。