公开(公告)号：US20160343607A1

公开(公告)日：2016-11-24

申请号：US14716938

申请日：2015-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Jer-Hueih(James) CHEN ,  Cuiqin XU ,  Padmaja NAGAIAH

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28 ,  H01L29/165 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/28008 ,  H01L21/3083 ,  H01L21/76232 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

Abstract translation: 形成在Si衬底的部分上延伸的自对准STI区域的方法，以便能够随后在不使用光刻掩模的情况下形成外延生长的嵌入式S / D区域，并且提供所得到的器件。 实施例包括在Si衬底上形成具有横向分开的开口的STI蚀刻掩模; 通过开口将浅沟槽形成Si衬底; 在浅沟槽和开口的相对侧壁上形成第一至第四氧化物间隔物; 在第一和第二氧化物间隔物之间​​以及第三和第四氧化物间隔物之间​​形成深的STI沟槽，进入Si衬底; 在所述第一至第四氧化物间隔物和所述STI蚀刻掩模的一部分上形成STI氧化物层，所述STI氧化物层填充所述深STI沟槽; 并且将STI氧化物层平坦化到STI蚀刻掩模的部分。

公开(公告)号：US20170125587A1

公开(公告)日：2017-05-04

申请号：US14926897

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mantavya SINHA ,  Prasanna KANNAN ,  Cuiqin XU ,  Tao WANG ,  Suresh Kumar REGONDA

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/7848 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/324 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847

Abstract: Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate having a channel region underlying, at least partially, the gate structure, the fabricating involving: performing a nitrogen ion implantation process by implanting nitrogen ions into the substrate to thereby form a stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and, with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region. In another embodiment, an amorphization ion implantation is performed prior to, after or along with the nitrogen ion implantation.

公开(公告)号：US20180286967A1

公开(公告)日：2018-10-04

申请号：US15997368

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Jer-Hueih(James) CHEN ,  Cuiqin XU ,  Padmaja NAGAIAH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/28 ,  H01L29/06 ,  H01L21/762 ,  H01L29/08 ,  H01L21/308

Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

公开(公告)号：US20150214330A1

公开(公告)日：2015-07-30

申请号：US14163687

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Jin Ping LIU ,  Guillaume BOUCHE ,  Andy WEI ,  Lakshmanan H. VANAMURTHY ,  Cuiqin XU ,  Sridhar KUCHIBHATLA ,  Rama KAMBHAMPATI ,  Xiuyu CAI

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31111 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.

Abstract translation: 一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。 去除层间电介质以露出第一间隔物。 去除第一间隔物并且在栅极的至少一侧沉积第二间隔物。 第二间隔物由具有比第一间隔物低的介电常数的材料形成。