公开(公告)号：US20150024585A1

公开(公告)日：2015-01-22

申请号：US13946485

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tien-Ying LUO ,  Feng ZHOU ,  Yan Ping SHEN ,  Haiting WANG ,  Haoran SHI ,  Wei Hua TONG ,  Seung KIM ,  Yong Meng LEE

IPC: H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28176 ,  H01L29/6659

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract translation: 一种方法包括通过在衬底上生长界面层来形成栅极结构，在界面层上沉积高K层，在高K层上沉积TiN帽并在TiN帽上形成薄的阻挡层。 栅极结构退火。

公开(公告)号：US20200035543A1

公开(公告)日：2020-01-30

申请号：US16047078

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Haiting WANG ,  Hong YU ,  Laertis ECONOMIKOS

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

公开(公告)号：US20190378763A1

公开(公告)日：2019-12-12

申请号：US16005073

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Ruilong XIE ,  Shesh Mani PANDEY ,  Hui ZANG ,  Garo Jacques DERDERIAN ,  Scott BEASOR

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/308 ,  H01L21/762 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.

公开(公告)号：US20200176444A1

公开(公告)日：2020-06-04

申请号：US16204506

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei XU ,  Hui ZANG ,  Ruilong XIE ,  Haiting WANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.

公开(公告)号：US20190109197A1

公开(公告)日：2019-04-11

申请号：US15728070

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Wei ZHAO ,  Hui ZANG ,  Hong YU ,  Zhenyu HU ,  Scott BEASOR ,  Erik GEISS ,  Jerome CIAVATTI ,  Jae Gon LEE

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

公开(公告)号：US20160190324A1

公开(公告)日：2016-06-30

申请号：US15059793

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua TONG ,  Tien-Ying LUO ,  Yan Ping SHEN ,  Feng ZHOU ,  Jun LIAN ,  Haoran SHI ,  Min-hwa CHI ,  Jin Ping LIU ,  Haiting WANG ,  Seung KIM

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

公开(公告)号：US20160049488A1

公开(公告)日：2016-02-18

申请号：US14458941

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping SHEN ,  Haiting WANG ,  Min-hwa CHI ,  Yong Meng LEE

IPC: H01L29/423 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/105 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L29/42376 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A semiconductor structure with wide-bottom and/or wide-top gates includes a semiconductor substrate, a source region(s), a drain region(s) associated with the source region(s), and a gate(s) associated with the source region(s) and the drain region(s) having a top portion and a bottom portion. One of the top portion and the bottom portion of the gate(s) is wider than the other of the top portion and bottom portion. The wide-bottom gate is created using a dummy wide-bottom gate etched from a layer of dummy gate material, creating spacers for the dummy gate, removing the dummy gate material and filling the opening created with conductive material. For the wide-top gate, first and second spacers are included, and instead of removing all the dummy gate material, only a portion is removed, exposing the first spacers. The exposed portion of the first spacers may either be completely or partially removed (e.g., tapered), in order to increase the area of the top portion of the gate to be filled.

Abstract translation: 具有宽底部和/或宽顶部栅极的半导体结构包括半导体衬底，源极区域，与源极区域相关联的漏极区域以及与所述源极区域相关联的栅极 源极区和漏极区具有顶部和底部。 栅极的顶部和底部之一比顶部和底部中的另一个宽。 使用从虚拟栅极材料层蚀刻的虚拟宽底栅极创建宽底栅极，产生用于伪栅极的间隔物，去除虚拟栅极材料并填充由导电材料形成的开口。 对于宽顶栅，包括第一和第二间隔物，而不是去除所有的虚拟栅极材料，仅去除一部分，暴露第一间隔物。 第一间隔件的暴露部分可以被完全或部分地去除（例如，渐缩），以增加要填充的浇口顶部的面积。

公开(公告)号：US20200335619A1

公开(公告)日：2020-10-22

申请号：US16386902

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping SHEN ,  Haiting WANG ,  Hui ZANG ,  Jiehui SHU

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.

公开(公告)号：US20190229183A1

公开(公告)日：2019-07-25

申请号：US15875132

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Hui ZANG ,  Chun Yu WONG ,  Kwan-Yong LIM

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762

Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.

公开(公告)号：US20150255277A1

公开(公告)日：2015-09-10

申请号：US14200197

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Hua TONG ,  Tien-Ying LUO ,  Yan Ping SHEN ,  Feng ZHOU ,  Jun LIAN ,  Haoran SHI ,  Min-hwa CHI ,  Jin Ping LIU ,  Haiting WANG ,  Seung KIM

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/324 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract translation: 提供具有一个或多个氮化保形层的鳍式晶体管制造方法和结构，以提高半导体器件的可靠性。 该方法包括例如提供至少一个材料层，该材料层部分地保形地设置在衬底上延伸的翅片上，所述材料层包括栅极电介质层; 以及在所述材料层的暴露表面上进行保形氮化处理，所述共形氮化工艺形成暴露的共形氮化表面。