公开(公告)号：US20130248982A1

公开(公告)日：2013-09-26

申请号：US13895197

申请日：2013-05-15

申请人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

发明人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7845 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7848

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

公开(公告)号：US08466513B2

公开(公告)日：2013-06-18

申请号：US13159255

申请日：2011-06-13

申请人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

发明人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

IPC分类号： H01L29/66

CPC分类号： H01L29/7845 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7848

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

摘要翻译： 在一个实施例中，垂直绝缘栅场效应晶体管包括嵌入在控制电极内的特征。 该特征被放置在控制电极内以在晶体管的预定区域内引起应力。

公开(公告)号：US08878286B2

公开(公告)日：2014-11-04

申请号：US13895197

申请日：2013-05-15

申请人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

发明人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417

CPC分类号： H01L29/7845 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7848

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

摘要翻译： 在一个实施例中，垂直绝缘栅场效应晶体管包括嵌入在控制电极内的特征。 该特征被放置在控制电极内以在晶体管的预定区域内引起应力。

公开(公告)号：US20120313161A1

公开(公告)日：2012-12-13

申请号：US13159255

申请日：2011-06-13

申请人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

发明人： Gordon M. Grivna ,  Zia Hossain ,  Kirk K. Huang ,  Balaji Padmanabhan ,  Francine Y. Robb ,  Prasad Venkatraman

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7845 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7848

摘要： In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

摘要翻译： 在一个实施例中，垂直绝缘栅场效应晶体管包括嵌入在控制电极内的特征。 该特征被放置在控制电极内以在晶体管的预定区域内引起应力。

公开(公告)号：US20100237409A1

公开(公告)日：2010-09-23

申请号：US12790987

申请日：2010-06-01

申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

公开(公告)号：US20080258210A1

公开(公告)日：2008-10-23

申请号：US11737923

申请日：2007-04-20

申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

公开(公告)号：US08035161B2

公开(公告)日：2011-10-11

申请号：US12790987

申请日：2010-06-01

申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

公开(公告)号：US07767529B2

公开(公告)日：2010-08-03

申请号：US11737923

申请日：2007-04-20

申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

IPC分类号： H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

公开(公告)号：US08207035B2

公开(公告)日：2012-06-26

申请号：US12696816

申请日：2010-01-29

申请人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

发明人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/66734

摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

摘要翻译： 在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。 垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。

公开(公告)号：US07714381B2

公开(公告)日：2010-05-11

申请号：US11095135

申请日：2005-04-01

申请人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

发明人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

IPC分类号： H01L27/105

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/66734

摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

摘要翻译： 在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。 垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。