利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

43 条记录 (耗时 0.028 秒)

    SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
    1.
    发明申请
    SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
    半导体元件及其制造方法

    公开(公告)号：US20080258210A1

    公开(公告)日：2008-10-23

    申请号：US11737923

    申请日：2007-04-20

    申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

    摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

    SEMICONDUCTOR COMPONENT
    2.
    发明申请
    SEMICONDUCTOR COMPONENT 有权
    半导体元件

    公开(公告)号：US20100237409A1

    公开(公告)日：2010-09-23

    申请号：US12790987

    申请日：2010-06-01

    申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

    摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

    Semiconductor component
    3.
    发明授权
    Semiconductor component 有权
    半导体元件

    公开(公告)号：US08035161B2

    公开(公告)日：2011-10-11

    申请号：US12790987

    申请日：2010-06-01

    申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00

    CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

    摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

    Semiconductor component and method of manufacture
    4.
    发明授权
    Semiconductor component and method of manufacture 有权
    半导体元件及制造方法

    公开(公告)号：US07767529B2

    公开(公告)日：2010-08-03

    申请号：US11737923

    申请日：2007-04-20

    申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

    摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

    Power efficient read circuit for a serial output memory device and method
    9.
    发明申请
    Power efficient read circuit for a serial output memory device and method 有权
    用于串行输出存储器件和方法的高效读取电路

    公开(公告)号：US20060039217A1

    公开(公告)日：2006-02-23

    申请号：US10921754

    申请日：2004-08-17

    申请人： Neal Berger ,  George Chang ,  Pearl Cheng ,  Anne Koh

    发明人： Neal Berger ,  George Chang ,  Pearl Cheng ,  Anne Koh

    IPC分类号： G11C7/00

    CPC分类号： G11C7/08 ,  G11C7/1027 ,  G11C7/103

    摘要： An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit. The control circuit receives a read command, and a clock signal, and in response to the read command activates a first plurality (j) of the plurality (k) of sense amplifiers (j

    摘要翻译： 集成电路存储器件具有以多个阵列排列的多个存储单元。 每个阵列具有多个行，多个列线以及连接到每个阵列中的存储器单元的多条行线。 阵列中的存储单元可由列线和行行寻址。 列地址解码器接收列地址信号并且响应地选择每个阵列的一个或多个列线。 行地址解码器接收行地址信号并且响应地选择每个阵列的行线。 存储器件还具有多个（k）个读出放大器，其中一个读出放大器与每个阵列相关联，可连接到阵列的一个或多个列线，并接收从寻址的存储器单元提供的信号。 存储器件还具有寄存器; 和控制电路。 控制电路接收读取命令，并且时钟信号，并且响应于读取命令，激活多个（k）个读出放大器（k）中的第一个（j）一段足以感测信号的时间段 在与多个（j）个读出放大器中的每一个相关联的连接列线上。 控制电路将信号锁存到寄存器中; 并且去激活所述第一多个（j）读出放大器; 并响应于时钟信号串行输出来自寄存器的信号。