公开(公告)号：US20100237409A1

公开(公告)日：2010-09-23

申请号：US12790987

申请日：2010-06-01

申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

公开(公告)号：US20080258210A1

公开(公告)日：2008-10-23

申请号：US11737923

申请日：2007-04-20

申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

公开(公告)号：US08035161B2

公开(公告)日：2011-10-11

申请号：US12790987

申请日：2010-06-01

申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

公开(公告)号：US07767529B2

公开(公告)日：2010-08-03

申请号：US11737923

申请日：2007-04-20

申请人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

发明人： Prasad Venkatraman ,  Gordon M. Grivna ,  Francine Y. Robb ,  George Chang ,  Carroll Casteel

IPC分类号： H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor component resistant to the formation of a parasitic bipolar transistor and a method for manufacturing the semiconductor component using a reduced number of masking steps. A semiconductor material of N-type conductivity having a region of P-type conductivity is provided. A doped region of N-type conductivity is formed in the region of P-type conductivity. Trenches are formed in a semiconductor material and extend through the regions of N-type and P-type conductivities. A field oxide is formed from the semiconductor material such that portions of the trenches extend under the field oxide. The field oxide serves as an implant mask in the formation of source regions. Body contact regions are formed from the semiconductor material and an electrical conductor is formed in contact with the source and body regions. An electrical conductor is formed in contact with the backside of the semiconductor material.

摘要翻译： 能够抑制寄生双极型晶体管的形成的半导体元件和使用减少数量的掩模步骤来制造半导体元件的方法。 提供具有P型导电性区域的N型导电性的半导体材料。 在P型导电性区域形成N型导电性的掺杂区域。 沟槽形成在半导体材料中并延伸通过N型和P型导电性的区域。 由半导体材料形成场氧化物，使得沟槽的部分在场氧化物的下方延伸。 场氧化物在源区的形成中用作注入掩模。 主体接触区域由半导体材料形成，并且形成与源区和身体区域接触的电导体。 形成与半导体材料的背面接触的电导体。

公开(公告)号：US20140252409A1

公开(公告)日：2014-09-11

申请号：US13794038

申请日：2013-03-11

申请人： Gary H. Loechelt ,  Carroll Casteel

发明人： Gary H. Loechelt ,  Carroll Casteel

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H02M1/32 ,  H02M3/1588 ,  H02M7/538 ,  H03K17/0814 ,  H03K17/162 ,  H03K17/74

摘要： A circuit can include a pair of switching elements that have terminals electrically connected to terminals of a power supply and have other terminals electrically connected to an output terminal. The circuit can include rectifying elements and one or more charge storage elements. The circuit may be used as a Buck converter. The rectifying element(s) and charge storage element(s) may help to reduce ringing at an output terminal of the circuit during normal operation and reduce the likelihood of exceeding a breakdown voltage between current-carrying electrodes of a switching element within the circuit during a switching operation.

摘要翻译： 电路可以包括一对开关元件，其具有电连接到电源的端子的端子，并且其他端子电连接到输出端子。 电路可以包括整流元件和一个或多个电荷存储元件。 该电路可以用作降压转换器。 整流元件和电荷存储元件可以有助于在正常操作期间减少电路的输出端子处的振铃，并且减小在电路内的开关元件的载流电极之间的击穿电压的可能性 切换操作。

公开(公告)号：US4574469A

公开(公告)日：1986-03-11

申请号：US650964

申请日：1984-09-14

申请人： Sal Mastroianni ,  Carroll Casteel ,  Terry S. Hulseweh

发明人： Sal Mastroianni ,  Carroll Casteel ,  Terry S. Hulseweh

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/223 ,  H01L21/31 ,  H01L21/74

CPC分类号： H01L21/76216 ,  Y10S148/035 ,  Y10S148/083 ,  Y10S148/086 ,  Y10S148/117 ,  Y10S148/122 ,  Y10S438/969

摘要： A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.

摘要翻译： 描述了用于在公共衬底中制造隔离半导体器件的工艺，其具有自对准和预定位的隔离壁，掩埋层和通道停止。 隔离壁由掺杂的通道阻挡区域上方的电介质区域和非单晶半导体区域的堆叠布置形成。 单个掩模层确定隔离壁的非单晶部分，通道停止部和掩埋层的位置和间隔。

公开(公告)号：US4583282A

公开(公告)日：1986-04-22

申请号：US650969

申请日：1984-09-14

申请人： Terry S. Hulseweh ,  Carroll Casteel

发明人： Terry S. Hulseweh ,  Carroll Casteel

IPC分类号： H01L21/033 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/80 ,  H01L21/76

CPC分类号： H01L21/763 ,  H01L21/033 ,  H01L21/74 ,  H01L21/76216 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/125 ,  Y10S148/128 ,  Y10S438/969

摘要： A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a polycrystalline semiconductor region, above a doped channel-stop region which acts as a field guard. A single mask layer determines the location and spacing of the buried portions of the isolation walls, the channel-stops, and the buried layers.

摘要翻译： 描述了用于在公共衬底中制造隔离半导体器件的工艺，其具有自对准和预定位的隔离壁，掩埋层和通道停止。 隔离壁由介质区域和多晶半导体区域的堆叠布置形成，该区域用作场防护体的掺杂通道阻挡区域上方。 单个掩模层确定隔离壁，通道停止物和掩埋层的掩埋部分的位置和间隔。