公开(公告)号：US20240402572A1

公开(公告)日：2024-12-05

申请号：US18328555

申请日：2023-06-02

Applicant: Hewlett Packard Enterprise Development LP

Inventor： XIAN XIAO ,  Thomas Van Vaerenbergh ,  Raymond G. Beausoleil

IPC: G02F3/02

Abstract: Examples of the present technology provide “tensorized” integrated coherent Ising machines that improve scalability by leveraging a tensorized optical coupling matrix comprising layers of multi-wavelength photonic tensor-train (TT) cores cascaded together via passive optical cross-connects. A multi-wavelength photonic TT core may comprise a Mach Zehnder interferometer (MZI) mesh (i.e., a lattice/array of interconnected MZIs) that modulates the phase and/or amplitude of optical signals. Tensorized integrated CIMs of the present technology can achieve further scalability optimizations by implementing bistable Ising nodes via one or more multi-wavelength Ising node collections. A multi-wavelength Ising node collection may comprise a bistable Ising nodes implemented on a common MZI, where each bistable Ising node of the multi-wavelength Ising node collection is associated with a separate wavelength of light.

公开(公告)号：US11953766B2

公开(公告)日：2024-04-09

申请号：US17843352

申请日：2022-06-17

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Stanley Cheung ,  Geza Kurczveil ,  Yuan Yuan ,  Xian Xiao ,  Raymond G. Beausoleil

IPC: G02F1/017

CPC classification number: G02F1/01708

Abstract: Implementations disclosed herein provide for devices and methods for obtaining parity time (PT) symmetric directional couplers through improved phase tuning, along with separate optical gain and optical loss tuning. The present disclosure integrates phase tuning and optical gain/loss tuning structures into waveguides of directional couplers disclosed herein. In some examples, directional couplers disclosed herein integrate one or more hybrid metal-oxide-semiconductor capacitors (MOSCAPs) formed by a dielectric layer between two semiconductor layers that provide for phase tuning via plasma dispersion and/or carrier accumulation depending on voltage bias polarity, and one or more optically active medium that provide for optical gain or loss tuning depending on voltage bias polarity.

公开(公告)号：US10805004B2

公开(公告)日：2020-10-13

申请号：US16495187

申请日：2017-04-07

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Tsung Ching Huang ,  Rui Wu ,  Nan Qi ,  Mir Ashkan Seyedi ,  Marco Fiorentino ,  Raymond G. Beausoleil

IPC: H04B10/00 ,  H04B10/079 ,  H04B10/50 ,  H04B10/54 ,  H04J14/00

Abstract: Examples described herein relate to reducing a magnitude of a supply voltage for a circuit element of an optical transmitter device. In some such examples, the circuit element is a driving element that is to receive a first electrical data signal and to provide a second electrical data signal to an optical element that is to provide an optical data signal. A testing element is to compare the optical data signal to the first electrical data signal to determine whether the optical transmitter device meets a performance threshold. When the device meets the performance threshold, a regulating element is to reduce a magnitude of the supply voltage of the driving element.

公开(公告)号：US10795084B2

公开(公告)日：2020-10-06

申请号：US16666053

申请日：2019-10-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Di Liang ,  Geza Kurczveil ,  Raymond G. Beausoleil

IPC: G02B6/136 ,  G02B6/124 ,  H01S3/063 ,  H01S3/23 ,  H01S5/10 ,  H01S5/20 ,  H01S5/02 ,  G02B6/12 ,  G02B6/13 ,  G02B5/18 ,  G02B6/122 ,  G02B27/42

Abstract: A hybrid grating comprises a first grating layer composed of a first solid-state material, and a second grating layer over the first grating layer and composed of a second solid-state material, the second solid state-material being different than the first solid-state material and having a monocrystalline structure.

公开(公告)号：US20200003971A1

公开(公告)日：2020-01-02

申请号：US16023596

申请日：2018-06-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Ashkan Seyedi ,  Marco Florentino ,  Geza Kurczveil ,  Raymond G. Beausoleil

IPC: G02B6/42 ,  G02B6/32 ,  G02B6/30 ,  G02B6/124 ,  G02B6/34 ,  G02B6/12 ,  H01S5/0683

Abstract: Processes and apparatuses described herein reduce the manufacturing time, the cost of parts, and the cost of assembly per laser for photonic interconnects incorporated into computing systems. An output side of a laser assembly is placed against an input side of a silicon interposer (SiP) such that each pad in a plurality of pads positioned on the output side of the laser assembly is in contact with a respective solder bump that is also in contact with a corresponding pad positioned on the input side of the SiP. The laser assembly is configured to emit laser light from the output side into an input grating of the SiP. The solder bumps are heated to a liquid phase. Capillary forces of the solder bumps realign the laser assembly and the SiP while the solder bumps are in the liquid phase. The solder bumps are then allowed to cool.

公开(公告)号：US20190353981A1

公开(公告)日：2019-11-21

申请号：US16526973

申请日：2019-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Charles M. Santori ,  Jason Pelc ,  Ranojoy Bose ,  Cheng Li ,  Raymond G. Beausoleil

IPC: G02F3/00 ,  G02B6/12 ,  G02F3/02 ,  G02F1/35

Abstract: In the examples provided herein, an optical logic gate includes multiple couplers, where no more than two types of couplers are used in the optical logic gate, and further wherein the two types of couplers consist of: a 3-dB coupler and a weak coupler with a given transmission-to-reflection ratio. The optical logic gate also includes a first resonator, wherein the first resonator comprises a photonic crystal resonator or a nonlinear ring resonator, wherein in operation, the first resonator has a dedicated continuous wave input to bias a complex amplitude of a total field input to the first resonator such that the total field input is either above or below a nonlinear switching threshold of the first resonator, where the optical logic gate is an integrated photonic circuit.

公开(公告)号：US20190204507A1

公开(公告)日：2019-07-04

申请号：US16298415

申请日：2019-03-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Raymond G. Beausoleil ,  Marco Fiorentino ,  Jason Pelc ,  Charles M. Santori ,  Terrel L. Morris

IPC: G02B6/13 ,  G02B6/00 ,  G02B6/28 ,  G02B6/26 ,  G02B6/122 ,  H04B10/80 ,  G02B6/14

CPC classification number: G02B6/13 ,  G02B6/00 ,  G02B6/122 ,  G02B6/125 ,  G02B6/14 ,  G02B6/26 ,  G02B6/2804 ,  G02B6/30 ,  H04B10/801

Abstract: One example includes an apparatus that includes a plurality of input/output (I/O) ports and a body portion. The plurality of I/O ports can be arranged at a plurality of peripheral surfaces of the body portion. The body portion includes a solid dielectric material having a substantially constant index of refraction. The body portion also includes parallel planar surfaces spaced apart by and bounded by the plurality of peripheral surfaces. The solid dielectric material in the body portion can be writable via a laser-writing process to form an optical waveguide extending between a set of the plurality of I/O ports.

公开(公告)号：US20190089129A1

公开(公告)日：2019-03-21

申请号：US16132070

申请日：2018-09-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Di Liang ,  Geza Kurczveil ,  Raymond G. Beausoleil ,  Marco Fiorentino

IPC: H01S5/343 ,  H01S3/23 ,  H01S3/063 ,  H01S5/02 ,  H01S5/34 ,  H01S5/042 ,  H01S5/32 ,  H01S5/347 ,  H01S5/026 ,  H01S5/10

CPC classification number: H01S5/343 ,  H01S3/0637 ,  H01S3/2375 ,  H01S5/021 ,  H01S5/0216 ,  H01S5/0261 ,  H01S5/0424 ,  H01S5/1032 ,  H01S5/3211 ,  H01S5/3412 ,  H01S5/347

Abstract: An example method of manufacturing a semiconductor device. A first wafer may be provided that includes a first layer that contains quantum dots. A second wafer may be provided that includes a buried dielectric layer and a second layer on the buried dielectric layer. An interface layer may be formed on at least one of the first layer and the second layer, where the interface layer may be an insulator, a transparent electrical conductor, or a polymer. The first wafer may be bonded to the second wafer by way of the interface layer.

公开(公告)号：US10212497B2

公开(公告)日：2019-02-19

申请号：US15028529

申请日：2013-10-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Terrel Morris ,  Charles F. Clark ,  Raymond G. Beausoleil

IPC: H04J14/02 ,  H04L12/70 ,  H04J14/00 ,  H04Q11/00 ,  H04L12/947

Abstract: A hybrid circuit-packet switch device includes a packet switch and a circuit switch. The circuit switch selectively passes, under control of a control logic, incoming data received at an optical input of the hybrid circuit-packet switch device to the packet switch or an optical output of the hybrid circuit-packet switch device.

公开(公告)号：US20190005301A1

公开(公告)日：2019-01-03

申请号：US16109716

申请日：2018-08-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Chin-Hui Chen ,  Tsung-Ching Huang ,  Zhihong Huang ,  Raymond G. Beausoleil

IPC: G06K9/00

Abstract: In the examples provided herein, a vascular pattern recognition system integrated onto a portable card includes a vascular pattern detection system to obtain image data of blood vessels of a finger to be swiped across a detection area on the portable card, wherein the vascular pattern detection system includes a near infrared light source and an image sensor array. The vascular pattern recognition system also includes an image processor to process the image data to generate a scanned vascular pattern and compare the scanned vascular pattern to a pre-stored pattern stored on the portable card to authenticate the image data, and a security processor to generate a transaction code to authorize a transaction upon authentication of the image data.