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    Encrypting data units with a memristor array
    2.
    发明授权
    Encrypting data units with a memristor array 有权

    公开(公告)号：US12010211B2

    公开(公告)日：2024-06-11

    申请号：US17563814

    申请日：2021-12-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Amit S. Sharma

    IPC: H04L9/06

    CPC classification number: H04L9/0631

    Abstract: Systems and methods are provided for encrypting data in a memristor array. The data may be scrambled by multiplying an input data unit by another data unit, by multiplying each element of a first data unit by a different instance of a second data unit. The process continues until all elements of the first data unit are multiplied by a different instance of the second data unit. The elements of the data units may be represented by resistive values of a memristor array. The result of all of the above multiplication of different instances of the second data unit are a new set of data units. All of the resulting data units are added together by adding the currents associated with values of the memristors representing the resulting data units. The operation may be performed as a finite field computation, with the memristor array.

    Vertical JFET device for memristor array interface
    5.
    发明授权
    Vertical JFET device for memristor array interface 有权

    公开(公告)号：US11322545B2

    公开(公告)日：2022-05-03

    申请号：US17041382

    申请日：2018-04-27

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Amit S. Sharma ,  John Paul Strachan ,  Martin Foltin

    IPC: H01L29/66 ,  H01L21/02 ,  H01L27/24 ,  H01L29/161 ,  H01L29/808

    Abstract: Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.

    SELF-HEALING DOT-PRODUCT ENGINE
    6.
    发明申请
    SELF-HEALING DOT-PRODUCT ENGINE 审中-公开

    公开(公告)号：US20200312406A1

    公开(公告)日：2020-10-01

    申请号：US16364717

    申请日：2019-03-26

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

    IPC: G11C13/00 ,  G06F11/10 ,  G11C29/52 ,  G06N3/04

    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

    CROSSPOINT ARRAY DECODER
    7.
    发明申请
    CROSSPOINT ARRAY DECODER 审中-公开

    公开(公告)号：US20170287540A1

    公开(公告)日：2017-10-05

    申请号：US15507790

    申请日：2014-09-25

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Brent Buchanan ,  Amit S. Sharma ,  Gary Gibson ,  Erik Ordentlich ,  Naveen Muralimanohar

    IPC: G11C8/10 ,  G11C13/00

    CPC classification number: G11C8/10 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028

    Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, a drain voltage is applied to a drain terminal of a field effect transistor switch for a selected row in the crosspoint array associated with the selected memory element. A bulk terminal of the field effect transistor switch for the selected row can be biased with a well voltage that is independent of the drain, source, or substrate voltages. In such examples, the gate terminal of the field effect transistor switch for the selected row can be driven with a gate voltage comprising the drain voltage and the well voltage. The drain voltage, the well voltage, and the gate voltage are selected to cause the field effect transistor switch for the selected row to operate as an ohmic switch.

    Self-healing dot-product engine
    9.
    发明授权
    Self-healing dot-product engine 有权

    公开(公告)号：US11532356B2

    公开(公告)日：2022-12-20

    申请号：US17223435

    申请日：2021-04-06

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Amit S. Sharma ,  John Paul Strachan ,  Catherine Graves ,  Suhas Kumar ,  Craig Warner ,  Martin Foltin

    IPC: G11C13/00 ,  G06N3/04 ,  G11C29/52 ,  G06F11/10

    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

    VERTICAL JFET DEVICE FOR MEMRISTOR ARRAY INTERFACE
    10.
    发明申请
    VERTICAL JFET DEVICE FOR MEMRISTOR ARRAY INTERFACE 有权

    公开(公告)号：US20210036058A1

    公开(公告)日：2021-02-04

    申请号：US17041382

    申请日：2018-04-27

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Amit S. Sharma ,  John Paul Strachan ,  Martin Foltin

    IPC: H01L27/24 ,  H01L29/161 ,  H01L29/808 ,  H01L21/02 ,  H01L29/66

    Abstract: Devices and methods are provided, In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.

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