公开(公告)号：US20060008042A1

公开(公告)日：2006-01-12

申请号：US11225600

申请日：2005-09-13

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Paul Owczarski ,  Martin Schmatz ,  Joseph Stevens

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Paul Owczarski ,  Martin Schmatz ,  Joseph Stevens

IPC分类号： H03D3/24

CPC分类号： H03L7/0995 ,  H04L7/0004 ,  H04L7/0337

摘要： The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

摘要翻译： 本发明涉及包括逻辑发射机部分和逻辑接收机部分的统一数字架构。 提供了一种用于在包括发射机和接收机部分的有线媒体上传输数字数据的统一的串行链路系统和方法，发射机部分和接收机部分之一包括锁相环（PLL）电路。 PLL电路包括压控振荡器，分频器，相频检测器，电荷泵和多极环路滤波器。 一个实施例包括具有数字粗略回路和模拟精细回路的双回路PLL。

公开(公告)号：US20050046489A1

公开(公告)日：2005-03-03

申请号：US10650396

申请日：2003-08-28

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Todd Rasmus ,  Peter Seidel

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Todd Rasmus ,  Peter Seidel

IPC分类号： H03L7/08 ,  H03L7/00

CPC分类号： H03L7/08 ,  H03L2207/06

摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

摘要翻译： 公开了一种用于锁相环的自适应电压调节器。 锁相环包括相位检测器，电荷泵，低通滤波器和压控振荡器，其中低通滤波器将控制电压输入到压控振荡器以产生输出时钟。 根据本文公开的方法和系统，自适应电压调节器耦合到低通滤波器的输出，用于在锁相环的正常操作期间感测控制电压，并且用于动态调整供电电压，即 响应于控制电压输入到压控振荡器，使得锁相环将控制电压保持在参考电压的预定范围内。

公开(公告)号：US20070069793A1

公开(公告)日：2007-03-29

申请号：US11235758

申请日：2005-09-27

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Samuel Ray ,  Wayne Utter

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Samuel Ray ,  Wayne Utter

IPC分类号： G06F1/04

CPC分类号： G06F1/04

摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

摘要翻译： 提供了一种差分时钟信号门控方法和系统，其中时钟缓冲器电路控制路径产生与时钟信号的定时关系的时钟门控信号。 时钟门控信号将响应于第一时钟信号脉冲负半部分的与时钟信号通信的时钟缓冲器电路控制路径上的缓冲器门控。 缓冲器提供在第一时钟信号脉冲之后立即和顺序发生的第二和连续时钟信号脉冲，作为输出到第二级时钟路径中的第二缓冲级的缓冲时钟信号，每个具有标称时钟幅度和标称时钟脉冲宽度 时钟信号无抖动。

公开(公告)号：US20070279117A1

公开(公告)日：2007-12-06

申请号：US11769408

申请日：2007-06-27

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Samuel Ray ,  Wayne Utter

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Samuel Ray ,  Wayne Utter

IPC分类号： H03K3/00

CPC分类号： G06F1/04

摘要： A differential clock signal gating method and system is provided, providing a clock gating signal with a timing relationship to a clock signal and a differential pair current to a buffer differential pair load element. Switching the differential pair current from the load element to a buffer differential pair responsive to a gating signal pulse, the gating signal pulse correlated to a first clock signal pulse, the buffer differential pair buffers a second clock signal pulse occurring immediately and sequentially after the first clock signal pulse and successive clock signal pulses as a buffer clock signal output, the output comprising a plurality of pulses each having the clock signal amplitude and the clock signal pulse width.

摘要翻译： 提供差分时钟信号门控方法和系统，提供具有与时钟信号的时序关系的时钟选通信号和到缓冲器差分对负载元件的差分对电流。 响应于门控信号脉冲将差分对电流从负载元件切换到缓冲差分对，门控信号脉冲与第一时钟信号脉冲相关，缓冲差分对缓冲在第一时钟信号脉冲之后立即和顺序发生的第二时钟信号脉冲 时钟信号脉冲和连续时钟信号脉冲作为缓冲时钟信号输出，所述输出包括多个脉冲，每个脉冲具有时钟信号幅度和时钟信号脉冲宽度。

公开(公告)号：US20070254613A1

公开(公告)日：2007-11-01

申请号：US11411662

申请日：2006-04-26

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman

IPC分类号： H04B7/00

CPC分类号： H03L7/18 ,  H03L7/0891

摘要： A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter nodes and thus centers the frequency of the VCO before stepping from one frequency band to the next.

摘要翻译： 用于跟踪VCO校准的电路设计，方法和系统，而不需要如常规实现中的过度设计的分频器。 滤波器复位分量被添加到VCO的输入端。 在校准机构/过程中添加了一个处理步骤，该校准机构/过程使滤波器节点短路，并因此在从一个频带到下一个频带之前将VCO的频率居中。

公开(公告)号：US20050077936A1

公开(公告)日：2005-04-14

申请号：US10685022

申请日：2003-10-14

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Todd Rasmus

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Todd Rasmus

IPC分类号： H03L7/10 ,  H03L7/00

CPC分类号： H03L7/10

摘要： Aspects for reducing jitter in a PLL of a high speed serial link are described. The aspects include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.

摘要翻译： 描述了降低高速串行链路的PLL抖动的方面。 这些方面包括检查与PLL中的压控振荡器（VCO）的性能有关的至少一个参数，以及基于检查来控制对VCO的电源电压的调节。 调节器控制电路进行检查和控制。

公开(公告)号：US20070268065A1

公开(公告)日：2007-11-22

申请号：US11835298

申请日：2007-08-07

申请人： Hayden Cranford, Jr. ,  Stacy Garvin ,  Todo Rasmus

发明人： Hayden Cranford, Jr. ,  Stacy Garvin ,  Todo Rasmus

IPC分类号： G05F3/02

CPC分类号： H03K17/161 ,  H03K2217/0018

摘要： A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

摘要翻译： 一种具有基于晶体管的开关拓扑的电路器件，其基本上消除了器件闭锁的可能性。 串联的低电压阈值（LVT）N沟道晶体管和上拉电阻跨越开关（P沟道）晶体管耦合，以便为开关晶体管提供一体的主体连接，开关晶体管连接 开关晶体管连接到LVT晶体管的上拉电阻和源极端子之间的一个节点。 LVT晶体管的栅极和漏极端子连接到开关晶体管的输出端子。 电阻器的另一端连接到开关晶体管的电源侧端子。 在特定配置中添加这些组件允许开关晶体管的主体连接自动切换到最高电位扩散节点。

公开(公告)号：US20070096792A1

公开(公告)日：2007-05-03

申请号：US11263008

申请日：2005-10-31

申请人： Hayden Cranford ,  Stacy Garvin ,  Todd Rasmus

发明人： Hayden Cranford ,  Stacy Garvin ,  Todd Rasmus

IPC分类号： H03K17/00

CPC分类号： H03K17/161 ,  H03K2217/0018

摘要： A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

公开(公告)号：US20050040898A1

公开(公告)日：2005-02-24

申请号：US10644374

申请日：2003-08-20

申请人： Stacy Garvin

发明人： Stacy Garvin

IPC分类号： H03K3/03 ,  H03K3/356 ,  H03K5/00 ,  H03L7/00

CPC分类号： H03K3/0322 ,  H03K3/356113 ,  H03K2005/00032 ,  H03K2005/00234

摘要： The present invention describes aspects of adjusting a frequency range of a delay cell of a VCO. The aspects include providing a CMOS latch of predetermined gain, and altering transconductance in the CMOS latch to alter a frequency range of the CMOS latch without altering the predetermined gain. The alteration of transconductance includes coupling at least one pair of series connected transistors in parallel with each switching device of the CMOS latch.