摘要:
Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.
摘要:
A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region. The dopant concentration level peak of the dopants forming the buried P well in the substrate will be located below the dopant concentration level peak of the N well a minimum distance sufficient to inhibit reduction of the effective depth of the N well, and a maximum distance not exceeding the maximum distance which will still provide enhanced latchup protection to one or more transistors formed in the CMOS region.
摘要:
Provided is a technique for fabrication of a nitrided gate oxide and shallow trench isolation (STI) oxide liner in a semiconductor depletion into STI oxide and the RNCE in CMOS devices by introducing nitrogen to the STI edges of the p-well. This technique improves isolation performance and is also effective to harden the oxide to reduce boron penetration. Nitridization of the STI liner may be conducted on its own or in combination with gate oxide nitridization, both with beneficial effect with regard to the RNCE. The nitridization may also be focussed on the channel region of the gate oxide in particular in order to mitigate RSCE.
摘要:
Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.
摘要:
An isolation trench in a silicon semiconductor substrate is provided with a barrier region containing nitrogen atoms formed in the trench, contiguous with the silicon semiconductor substrate surfaces of the trench. The novel isolation trench structure of the invention is formed by forming an isolation trench in a silicon semiconductor substrate; forming in the isolation trench a barrier region by treating the trench structure with nitrogen atoms from a nitrogen plasma; and then forming a silicon oxide layer over the barrier region in the trench to confine the nitrogen atoms in the barrier region. In a preferred embodiment, a silicon oxide liner is first formed over the silicon semiconductor substrate surfaces of the trench, and then the trench structure is treated with nitrogen atoms from a nitrogen plasma to form, on the silicon semiconductor substrate surfaces of the trench, a barrier layer which contains silicon atoms, oxygen atoms, and nitrogen atoms.
摘要:
A device can include a controller interface having at least one controller data output configured to output read data, and at least one controller data input configured to receive write data; and a memory device interface having a write data output configured to transmit the write data on rising and falling edges of a periodic signal, and a read data input configured to receive the read data at a same transmission rate as the write data.
摘要:
Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substrate and subsequently etching a recess in exposed portions of the substrate. In some cases, the method includes forming a first dopant region within the exposed portions prior to etching the recess. The method may additionally or alternatively include implanting a second set of dopants into portions of the semiconductor substrate bordering the recess. In either case, the method includes growing an epitaxial layer within the recess and implanting a third set of dopants into the semiconductor topography to form a second dopant region extending to a depth at least within the epitaxial layer. A resulting semiconductor topography includes a source/drain region comprising an upper portion consisting essentially of first dopants of a first conductivity type.
摘要:
A method of forming a narrow isolation structure in a semiconducting substrate. The isolation structure is a trench that has a bottom and sidewalls, and that is to be filled with an isolating material. The isolating material has desired electrical properties and desired chemical properties, and is substantially reactively grown from the semiconducting substrate. A precursor material layer is formed on the bottom of the trench and on the sidewalls of the trench. The precursor material layer has electrical properties and chemical properties that are substantially similar to the desired electrical properties and the desired chemical properties of the isolating material. A substantial portion of the precursor material layer is removed from the bottom of the trench to expose the semiconducting substrate at the bottom of the trench, while leaving a substantial portion of the precursor material layer on the sidewalls of the trench. The isolating material is reactively grown in the trench, where the isolating material preferentially grows from the exposed semiconducting substrate at the bottom of the trench at a first rate. The precursor material layer at least partially inhibits formation of the isolating material from the semiconducting substrate at the sidewalls of the trench. The isolating material forms from the sidewalls of the trench at a second rate, where the first rate is substantially higher than the second rate. Thus, by forming a precursor layer that inhibits formation of the isolation material at the sidewalls of the trench, the isolation material preferentially grows from the bottom of the trench rather than expanding sideways from the sidewalls of the trench, which tends to widen the isolation structure. Because the precursor layer has properties that are substantially similar to those that are desired in the isolation material, the precursor layer remains at the sidewalls of the trench near the edge of the isolation structure. Therefore, the isolation structure functions as desired, but is narrower than it otherwise would be, if the precursor layer had not been formed.
摘要:
A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.
摘要:
A voltage protection device and method is provided to prevent accidental triggering of an silicon-controlled rectifier (SCR) unless the electrostatic discharge (ESD) is at a predefined threshold above the normal power supply operating voltage or below the ground supply operating voltage. The holding voltage upon the SCR is maintained above the threshold voltage to prevent accidental triggering. The present SCR avoids use of an additional field effect transistor (FET), and avoids relying upon the breakdown of the drain terminal of the FET, but instead programs the amount of holding voltage needed above the power supply voltage using mask-programmability, fuses, or other means for maintaining the holding voltage to a desired range above the power supply voltage. The programmed holding voltage is implemented using a barrier region between the PNP and the NPN of the PNPN junctions of the SCR. In addition to or as an alternative to the barrier region, hole sink junctions can be implemented close to the anode to reduce the substrate resistance in the vicinity of the anode and, therefore, extract holes from their normal target destination.