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    Base station control apparatus and base station control method
    8.
    发明授权
    Base station control apparatus and base station control method 有权
    基站控制装置和基站控制方法

    公开(公告)号：US08190106B2

    公开(公告)日：2012-05-29

    申请号：US12443729

    申请日：2008-06-04

    申请人： Hiroaki Miyamoto

    发明人： Hiroaki Miyamoto

    IPC分类号： H04B1/04 ,  H04B1/00 ,  H04B15/00 ,  H04B17/00 ,  H03C1/62 ,  H04W4/00 ,  H04W36/00

    CPC分类号： H04W72/082 ,  H04W16/28 ,  H04W72/12

    摘要： There is provided a base station control apparatus and a base station control method in which a frame is segmented in a situation in which interference may occur. A BS controller divides and controls a base station into three sectors and controls communications with terminal stations (TSs). A control unit determines whether or not the TS is in at least any of a state in which the TS is interfered within a certain sector by any other sector and a state in which the TS is located in a boundary between a plurality of sectors, and segments a communication frame for a TS which is determined as being in at least any of a state in which the TS is interfered within a certain sector by any other sector and a state in which the TS is located in a boundary between a plurality of sectors.

    摘要翻译： 提供了一种基站控制装置和基站控制方法，其中在可能发生干扰的情况下对帧进行分段。 BS控制器将基站分割并控制为三个扇区，并控制与终端站（TS）的通信。 控制单元确定TS是否处于其中TS在某个扇区内被任何其他扇区干扰的状态和TS位于多个扇区之间的边界中的状态中的至少任一个，以及 划分一个TS的通信帧，该通信帧被确定为在任何其他扇区中TS在某个扇区内被干扰的状态中的至少任一个以及TS位于多个扇区之间的边界中的状态 。

    Memory construction apparatus for forming logical memory space
    9.
    发明授权
    Memory construction apparatus for forming logical memory space 失效
    用于形成逻辑存储空间的存储器构造装置

    公开(公告)号：US07805688B2

    公开(公告)日：2010-09-28

    申请号：US11698856

    申请日：2007-01-29

    申请人： Noritoshi Yamakawa ,  Hiroaki Miyamoto ,  Yoshikatsu Kouhara ,  Akitsugu Nakayama ,  Kouichi Tanda

    发明人： Noritoshi Yamakawa ,  Hiroaki Miyamoto ,  Yoshikatsu Kouhara ,  Akitsugu Nakayama ,  Kouichi Tanda

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical condition defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied. A circuit description-processing section executes circuit description by using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.

    摘要翻译： 逻辑存储器构造处理部分读取作为库预先准备的几种物理存储器和寄存器，通过仅结合物理存储器或仅存储寄存器或物理存储器和寄存器两者来产生每个逻辑存储器的候选，每个 构成满足定义存储器空间的逻辑条件的逻辑存储器，并且根据优先级从候选中选择逻辑存储器的最高优先级候选。 最佳构造提取处理部分从最高优先级候选中提取满足各个逻辑条件的最佳逻辑存储器，使得满足可用物理存储器和可用寄存器的限制数量。 电路描述处理部分通过使用构成每个提取的最佳逻辑存储器的物理存储器和寄存器来执行电路描述，从而生成电路描述文件。