公开(公告)号：US20230197528A1

公开(公告)日：2023-06-22

申请号：US18054228

申请日：2022-11-10

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Dunja Radisic ,  Bilal Chehab

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/522

CPC classification number: H01L21/823871 ,  H01L27/092 ,  H01L23/5226

Abstract: A method for forming an integrated circuit. The method includes providing a semiconductor structure comprising: (i) two transistors, (ii) a gate on the channel of the transistor, (iii) contacts coupled to each transistor, (iv) a dielectric layer over the two transistors, the gate, and the contacts, (v) a first conductive line arranged within a first metallization level and extending along a first direction, (vi) a first conductive via connecting the first conductive line with a first contact of a transistor, and (vii) a second conductive via connecting the first conductive line with a second contact of a transistor. The method also includes recessing the first dielectric layer, providing spacers along the first conductive line, depositing a second dielectric layer on the first dielectric layer, forming an opening in the second dielectric layer and first dielectric layer, and providing a conductive material in the opening, thereby forming a third conductive via.

公开(公告)号：US20240204082A1

公开(公告)日：2024-06-20

申请号：US18543933

申请日：2023-12-18

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Boon Teik Chan ,  Shairfe Muhammad Salahuddin ,  Julien Ryckaert ,  Bilal Chehab ,  Hsiao-Hsuan Liu

IPC: H01L29/66 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/306 ,  H01L29/66439

Abstract: Example embodiments relate to methods for forming a semiconductor device. One example method includes forming a device structure on a substrate, where the device structure includes a device layer stack that includes a bottom device sub-stack that includes at least one bottom channel layer and a top device sub-stack that includes at least one top channel layer, a sacrificial gate structure extending across the device layer stack, and bottom source/drain structures on opposite ends of at least one bottom channel layer. The method also includes forming an opening exposing the top device sub-stack, wherein forming the opening includes etching the sacrificial gate structure, forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening and, subsequent to forming the cut, forming a functional gate stack on the at least one bottom channel layer.

公开(公告)号：US20230178629A1

公开(公告)日：2023-06-08

申请号：US18060945

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Geert Hellings ,  Bilal Chehab ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L29/66439 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545

Abstract: A method is provided for forming a FET device. The method includes: forming a preliminary device structure comprising a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers, and a deposited layer along a first side of the fin structure and a dummy structure along a second side of the fin structure; forming a mask line; forming along a first side of the fin structure a source and drain trench in the deposited layer; forming a set of source and drain cavities in the layer stack, by etching the fin structure from the source trench and the drain trench; forming a source body and a drain body comprising a respective common body portion a set of prongs protruding from the respective common body portion into the source and drain cavities; embedding the mask line in a cover material and removing the mask structure; forming a gate trench by etching the dummy structure; forming a set of gate cavities in the layer stack by etching the fin structure from the gate trench; and forming a gate body comprising a common gate body portion in the gate trench and a set of gate prongs protruding from the common gate body portion into the gate cavities.

公开(公告)号：US20230197514A1

公开(公告)日：2023-06-22

申请号：US18066400

申请日：2022-12-15

Applicant: IMEC VZW

Inventor： Victor Hugo Vega Gonzalez ,  Bilal Chehab ,  Julien Ryckaert ,  Zsolt Tokei ,  Serge Biesemans ,  Naoto Horiguchi

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/5226 ,  H01L21/32136 ,  H01L27/092

Abstract: The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via. The method further includes providing a planar dielectric material in contact with the first electrically conductive line, forming an opening in the planar dielectric material, filling the opening with a planar electrically conductive material, forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material, providing a hard mask comprising a set of parallel lines, and etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.

公开(公告)号：US20230361205A1

公开(公告)日：2023-11-09

申请号：US18298820

申请日：2023-04-11

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Bilal Chehab ,  Julien Ryckaert

IPC: H01L29/775 ,  H01L27/085 ,  H01L29/423 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L29/775 ,  H01L27/085 ,  H01L29/42392 ,  H01L29/0673 ,  H01L23/5286

Abstract: A standard cell semiconductor device is provided that includes a first and second FET device, each including: (i) a source body and a drain body, each including a common source or drain body portion and a set of source or drain prongs protruding from the common source or drain body portion, (ii) a set of channel layers, each channel layer extending between a pair of source and drain prongs, and (iii) a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion.

公开(公告)号：US20230178554A1

公开(公告)日：2023-06-08

申请号：US18060785

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Bilal Chehab ,  Pieter Schuddinck ,  Julien Ryckaert ,  Pieter Weckx

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L23/528 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392

Abstract: Example embodiments relate to complementary field-effect transistor (CFET) devices. An example CFET device includes a bottom FET device. The bottom FET device includes a bottom channel nanostructure having a first side surface oriented in a first direction. The bottom FET device also includes a second side surface oriented in a second direction opposite the first direction. Further, the bottom FET device includes a bottom gate electrode configured to define a tri-gate or a gate-all-around with respect to the bottom channel nanostructure. The bottom gate electrode includes a side gate portion arranged along the first side surface of the bottom channel nanostructure. The CFET device also includes a top FET device stacked on the bottom FET device. The top FET device includes channel layers, a gate electrode, and gate prongs. Additionally, the CFET device includes a top gate contact via. Further, the CFET device includes a bottom gate contact via.