公开(公告)号：US20240036470A1

公开(公告)日：2024-02-01

申请号：US18356700

申请日：2023-07-21

Applicant: IMEC VZW

Inventor： Waikin Li ,  Zheng Tao

IPC: G03F7/11 ,  G03F7/00 ,  G03F1/38 ,  G03F1/56 ,  G03F7/09

CPC classification number: G03F7/11 ,  G03F7/0035 ,  G03F1/38 ,  G03F1/56 ,  G03F7/094

Abstract: A method is provided for forming an interconnect structure for an integrated circuit. The method includes: forming a metal layer over a substrate; forming a hard mask layer over the metal layer; forming a first resist layer of a first resist material over the hard mask layer and patterning the first resist layer in a first lithography process to define a first resist pattern; forming over the first resist pattern a second resist layer of a second resist material different from the first resist material and patterning the second resist layer in a second lithography process to define a second resist pattern of resist lines extending in parallel along a first direction, wherein at least a portion of the first resist pattern is overlapped by the second resist pattern; patterning the hard mask layer using the second resist pattern as an etch mask to define a hard mask line pattern underneath the second resist pattern, and subsequently the metal layer to define a metal line pattern underneath the hard mask line pattern; removing the second resist pattern and subsequently patterning the hard mask line pattern using said at least a portion of the first resist pattern as an etch mask to define a hard mask pillar pattern over the metal line pattern; and forming a metal pillar pattern in accordance with the hard mask pillar pattern.

公开(公告)号：US20190189458A1

公开(公告)日：2019-06-20

申请号：US16218749

申请日：2018-12-13

Applicant: IMEC VZW

Inventor： Waikin Li ,  Danilo De Simone ,  Sandip Halder ,  Frederic Lazzarino

IPC: H01L21/308 ,  G03F7/20

Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.

公开(公告)号：US11824122B2

公开(公告)日：2023-11-21

申请号：US17208800

申请日：2021-03-22

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0669 ,  H01L29/66545 ,  H01L29/66818

Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.

公开(公告)号：US20230207482A1

公开(公告)日：2023-06-29

申请号：US18068839

申请日：2022-12-20

Applicant: IMEC VZW

Inventor： Waikin Li ,  Zheng Tao ,  Min-Soo Kim

IPC: H01L23/544 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L29/7827 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/0669 ,  H01L22/20

Abstract: A semiconductor structure includes a device area that includes a first structure in a first layer having a top surface above a top surface of the first layer, and a second structure in a second layer on top of the first layer, where the first structure is pinned in the second structure; an overlay metrology area for optically evaluating an overlay error between the second and first structure, including: a third structure in the first layer, having a top surface above the top surface of the first layer, a fourth structure in the second layer, where the combination of the third and fourth structures mimics the combination of the first structure and the second structures, and a fifth structure in the first layer, for use as a reference structure.

公开(公告)号：US20230046117A1

公开(公告)日：2023-02-16

申请号：US17884870

申请日：2022-08-10

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Waikin Li

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/306 ,  H01L23/528 ,  H01L21/762

Abstract: A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

公开(公告)号：US11862452B2

公开(公告)日：2024-01-02

申请号：US17006642

申请日：2020-08-28

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L21/762 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/02 ,  H01L29/775 ,  H01L21/822 ,  H01L29/10 ,  H01L21/768

CPC classification number: H01L21/76224 ,  H01L21/02175 ,  H01L21/76834 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/775

Abstract: In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.

公开(公告)号：US20210296500A1

公开(公告)日：2021-09-23

申请号：US17208800

申请日：2021-03-22

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.

公开(公告)号：US20210066116A1

公开(公告)日：2021-03-04

申请号：US17006642

申请日：2020-08-28

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L21/762 ,  H01L27/092 ,  H01L29/06

Abstract: In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.

公开(公告)号：US10818504B2

公开(公告)日：2020-10-27

申请号：US16218749

申请日：2018-12-13

Applicant: IMEC VZW

Inventor： Waikin Li ,  Danilo De Simone ,  Sandip Halder ,  Frederic Lazzarino

IPC: H01L21/308 ,  G03F7/20 ,  G03F1/70

Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.