公开(公告)号：US12237207B2

公开(公告)日：2025-02-25

申请号：US18469374

申请日：2023-09-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez ,  Anshul Gupta ,  Basoene Briggs

IPC: H01L21/74 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535

Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

公开(公告)号：US20240170328A1

公开(公告)日：2024-05-23

申请号：US18514461

申请日：2023-11-20

Applicant: IMEC VZW

Inventor： Anshul Gupta ,  Zsolt Tokei ,  Stefan Decoster

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877

Abstract: A method includes forming and patterning a first dielectric over a substrate; covering the first dielectric with metal and planarizing the metal exposing a surface of the first dielectric and forming a first metal; forming a second dielectric over the first dielectric and the first metal; covering the second dielectric with metal and planarizing the metal exposing a surface of the second dielectric and forming a second metal; forming a mask over the second dielectric and the second metal; and transferring: a first sub-pattern of the mask into a first portion of the first metal to form a lower metal, a second sub-pattern of the mask into a first portion of the second metal and a second portion of the first metal to form a stacked metal, and a third sub-pattern of the mask into a second portion of the second metal to form an upper metal.

公开(公告)号：US20240006228A1

公开(公告)日：2024-01-04

申请号：US18469374

申请日：2023-09-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez ,  Anshul Gupta ,  Basoene Briggs

IPC: H01L21/74 ,  H01L21/8234 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/743 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/5286

Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

公开(公告)号：US20210035860A1

公开(公告)日：2021-02-04

申请号：US16945858

申请日：2020-08-01

Applicant: IMEC VZW

Inventor： Eugenio Dentoni Litta ,  Anshul Gupta ,  Julien Ryckaert ,  Boon Teik Chan

IPC: H01L21/768 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/8234

Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.

公开(公告)号：US12154830B2

公开(公告)日：2024-11-26

申请号：US17580020

申请日：2022-01-20

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Anshul Gupta ,  Geert Van Der Plas

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail.

公开(公告)号：US11335597B2

公开(公告)日：2022-05-17

申请号：US16945858

申请日：2020-08-01

Applicant: IMEC VZW

Inventor： Eugenio Dentoni Litta ,  Anshul Gupta ,  Julien Ryckaert ,  Boon Teik Chan

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234

Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.

公开(公告)号：US20250029872A1

公开(公告)日：2025-01-23

申请号：US18762318

申请日：2024-07-02

Applicant: IMEC VZW

Inventor： Anshul Gupta ,  Zsolt Tokei ,  Stefan Decoster ,  Gayle Murdoch ,  Seongho Park

IPC: H01L21/768 ,  H01L23/522

Abstract: Methods and systems for producing an interconnect via are provided. A conductive layer is produced on a substrate having an upper surface of a dielectric material with conductors or contacts embedded in the dielectric material. A dielectric layer is produced on the conductive layer. An opening is formed in the dielectric layer and filled with a conductive material to form a conductive via. The dielectric layer and the via are planarized to a common planar level. At least one hardmask line which overlaps the via is formed. The dielectric material and the conductive material of the via and of the conductive layer are removed in the areas not covered by the hardmask line, resulting in a conductive line having an interconnect via on its top surface. The interconnect via is aligned to the width of the conductive line. The hardmask line is removed and a planar dielectric surface is produced.

公开(公告)号：US20240203994A1

公开(公告)日：2024-06-20

申请号：US18543815

申请日：2023-12-18

Applicant: IMEC VZW

Inventor： Anshul Gupta ,  Hans Mertens

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/50

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/76805 ,  H01L23/50 ,  H01L29/66545

Abstract: The disclosure relates to a method for forming an integrated circuit device that includes forming a forksheet device on a frontside of a substrate, the forksheet device comprising a first and a second transistor separated by a vertically oriented dielectric wall, such that the forksheet device is formed over a base portion of the substrate and the dielectric wall extends into the base portion; subsequent to forming the forksheet device, thinning the substrate from a backside of the substrate; subsequent to the thinning, forming a first trench underneath the first transistor and a second trench underneath the second transistor by etching the base portion from the backside, the first and second trenches being separated by the dielectric wall; and forming a first backside wiring line in the first trench and a second backside wiring line in the second trench.

公开(公告)号：US10957575B2

公开(公告)日：2021-03-23

申请号：US16718624

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Dmitry Yakimets ,  Anshul Gupta

IPC: H01L21/70 ,  H01L21/74 ,  H01L21/311 ,  H01L21/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/535

Abstract: An integrated circuit chip having fin-based active devices in the front end of line, and an electrical connection between a buried interconnect rail and a contact area on a semiconductor fin, such as an epitaxially grown source or drain contact area of a transistor, is disclosed. In one aspect, the electrical connection is realized without the intervention of a metallization level formed above the active devices in the IC. Instead, an interconnect via is produced between the buried interconnect rail and a lateral portion of the contact area, wherein the lateral portion is directly contacted by a sidewall of the interconnect via. Methods for producing the interconnect via are also disclosed.

公开(公告)号：US20210028059A1

公开(公告)日：2021-01-28

申请号：US16934200

申请日：2020-07-21

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez ,  Anshul Gupta ,  Basoene Briggs

IPC: H01L21/768

Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.